Part Number: TMS320C6657
From Table 6-100 (C66x DSP System PLL Configuration() pg 191 of data sheet and after setting the strapping for BOOTMODE[12:10] to 0b011 for the 1250 MHz device I am given that PLLD = 0 PLL M = 24 and DSP fis 1250 MHz with an input clock frequency of 100 MHz.
....From reading section 2.2.1 page 2-4 of
KeyStone Architecture
Literature Number: SPRUGY5C
July 2013
DSP Bootloader
I find the following
The main PLL stays in bypass mode for no-boot, SPI, and I2C boot. For other boot
modes, a PLL initialization sequence executes inside the boot ROM to configure
the main PLL in PLL mode.
So i think that since Im using emif16 booting the pll is not bypassed.
From page 5,
KeyStone Architecture
Phase-Locked Loop (PLL)
I see a block diagram of the PLL From the diagram PLLENSRC controls a mux which I think i have seen implications but no direct statement that PLLENSRC is a high (1) and therfore the input clock which is 100 MHz in my case is routed directly to sysclk7 which is used for th emif booting. Sysclk7 at power up during booting then is 100 MHz/6....is this the correct frequency for sysclk7? Have I made the right deduction?......my main problem in being sure is I dont know what PLLENSRC is on power up. if its anything other than 1 then I would need to know what PLLen is on power up as well.
But if 100MHz/6 is sysclk7 which is the emif boot clock...how can i speed it up to ensure faster booting?
Thanks
