• State Resolved
  • Locked Locked
  • Replies 5 replies
  • Answers 2 answers
  • Subscribers 98 subscribers
  • Views 924 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM5728: Driving both PCIe ports simultaneously

Ivan Chousal
Intellectual 315 points
Part Number: AM5728

Hello, 

We have a need to drive two downstream PCIe subsystems simultaneously from the AM5728's PCIe interface.  In one case, we have a downstream system that uses the clock pair and one lane (i.e. clkp/n, Rx0_n/p, Tx0_n/p).  In the other case, we have a downstream system that only utilizes one lane without a clock (i.e. rx_pair1, tx_pair1 NO CLOCK).  Can TI confirm if the AM5728 is capable of driving these two configurations simultaneously as described above?  I've taken a quick snippet of the pinmux csv fill to show how we intend to connect the systems.

Thanks

  • 0
    TI__Guru**** 393215 points
    The PCIe experts have been notified. They will respond here.
  • 0 in reply to Biser Gatchev-XID
    TI__Guru* 95265 points
    Hi,

    In your case, there are two seperate PCIE controllers (SS1 and SS2) each controls one lane. The two controllers and clocks are independent. It is possible one controller downstream clock to EP, the other controller only downstream the data without clock.

    Regards, Eric
  • 0 in reply to lding
    Intellectual 315 points

    Hello Eric,

    Apologies, but It's still not clear from your response if it's ok to drive two downstream PCIe devices when one controller utilizes both clock and 1x data lane, while the other controller only uses the other 1x data lane.  In our case, the pinmux result only generated one clock... not two.  This is what's driving confusion.  You stated that there are "two controllers and two clocks that are independent."

    To recap, our goal is to have one full 1x lane PCIe interface using a standard PCIe connector.  The remaining 1x lane (i.e. rx/tx1) is to be wired separately to another connector for communication to a downstream board.  I just need confirmation from TI that it's possible to drive both standard PCIe interface at the same time we drive our downstream board which are two separate systems.  The pinmux result only generated 1 clk as shown below.  Please confirm.

    Thank you.

  • 0 in reply to Ivan Chousal
    Intellectual 745 points
    Hi Ivan,

    I'm NOT a TI employee, but from what I read and understood the system it should be possible to drive two devices with a single clock.

    The PCIe AM57x8 subsystem has a separate block for 100 MHz block generation for PCIe (ljcb_clkp, ljcb_clkn), so two downstream devices, which use PCIe_SS1 and PCIe_SS2 can use the same clock for synchronization.

    The other question is how you route your PCB (one clock patch is much longer than the other). In such a case you can use a PCIe clock buffer.

    BUT anyway, TI will for sure give you final answer.

    BR,
    Łukasz
  • 0 in reply to user4759774
    TI__Guru* 95265 points
    Lukasz, Thanks!

    Ivan, the AM572x has two PCIE controllers, each has its own clock. You can look at our example code pdk_am57xx_1_0_4\packages\ti\drv\pcie\example\sample\am57x\src\pcie_sample_board.c there are PlatformPCIESS1ClockEnable() and PlatformPCIESS2ClockEnable().

    You can have the same crystal on your board to generate input the two DPLLs, then the DPLL each used as the input to the APLL. Also, you can route only one of the 100MHz clock to ljcb_clkp and ljcb_clkn (see TRM Figure 24-160. PCIe Controller Subsystem Overview) via ACSPCIE.

    Regards, Eric