66AK2E05: Interrupts on ARM A15 noOS

Hannan Khan

Expert 1080 points

Part Number: 66AK2E05
Other Parts Discussed in Thread: SYSBIOS

Hi !!

this question has been asked before without a satisfactory answer so i want to ask once more

system = Bare Metal (i.e. no OS no sysbios etc)

now i am using the following directory

ti/pdk_k2e_4_0_2/packages/ti/csl/arch/a15 ===> provides me with basic interrupt handling

now as per the interrupt.h the "NUM_INTERRUPTS_EXTERNAL" = 160.

as per datasheet of K2E total interrupts = 480

for the 160 interrupts i have checked my code (shown below) to work easily

	Intc_Init();
intcnumb=120;
	stat=IntMasterStatusGet();
	IntMasterIRQEnable();
	Intc_SystemEnable(intcnumb);
	Intc_IntRegister(intcnumb, intIsr, NULL);
	stat=IntMasterStatusGet();

	a = 0;
	pinNum = 0;
	bankNum = 0;

	hGpio = CSL_GPIO_open (0);
	CSL_GPIO_setPinDirOutput (hGpio, pinNum);
    CSL_GPIO_setRisingEdgeDetect (hGpio, pinNum);
    CSL_GPIO_bankInterruptEnable (hGpio, bankNum);
    CSL_GPIO_clearOutputData (hGpio, pinNum);
    CSL_GPIO_getOutputData (hGpio, pinNum, &outData);
    CSL_GPIO_setOutputData (hGpio, pinNum);
    CSL_GPIO_getOutputData (hGpio, pinNum, &outData);

the interrupt here fires perfectly but when i try to configure any interrupt above the NUM_INTERRUPTS_EXTERNAL, as mentioned above, the interrupt doesn't trigger. this is because the interrupt.c in the directory mentioned above has a check if (intrNum < NUM_INTERRUPTS_EXTERNAL) but even if i do bypass this condition i am still not able to configure the interrupts which leaves me with 2 choices

1. i map the interrupt (for example int numb 277) to something in the range of 160

2. there is a register which allows me to access interrupts with >160

in either case i am lost at how to approach this problem

just for a reminder the system is bare metal ARM core 0

over 8 years ago

0 Cvetolin Shulev-XID over 8 years ago

TI__Guru 65405 points

Hi Hannan,

I've forwarded this to the experts. Their feedback should be posted here.

BR
Tsvetolin Shulev

0 ran35366 over 8 years ago in reply to Cvetolin Shulev-XID

TI__Genius 12805 points

Hi Hannan

You mention an earlier posting. Can you send me the URL?

You are right, the number of events in K2E is 480. I think that the 160 limitation might be a bug when the code was ported from a different device (AM57X) that has only 160 event. I will investigate this further and may submit a report.

I wonder what event you try to connect - is it even 277 of the GIU (table 7-23 of www.ti.com/.../66ak2e05.pdf ) or the CIC2 (table 7-25 of the same document). If this is the later, then mapping of the CIC2 is required.

Get back to me and then we will continue

Regards

Ran

0 Hannan Khan over 8 years ago in reply to ran35366

Expert 1080 points

hello Ran !!

first of all i was looking at the UART interrupt (277 to 279) as seen in the table 7-23. i was working with UART because i was able to look directly at memory level that the interrupt was indeed fired by the UART but wasnt responded to by the arm.

now i might add a couple of things here which probably wont help but might tell you where i am messing things up. i have looked at 2 methods 1 of which is mentioned above the other is the HwiP_nonos located at ..../ti/pdk_k2e_4_0_2/packages/ti/osal/src/nonos but due to lack of documentations and examples i wasnt able to explore this much.

also here are the links to my interrupt queries
e2e.ti.com/.../559243
e2e.ti.com/.../551196
e2e.ti.com/.../2015142

best regards ,
Hannan

0 ran35366 over 8 years ago in reply to Hannan Khan

TI__Genius 12805 points

I think that this is a bug. I reported it to engineering and I will update you with their response

Meanwhile, did you consider using the DSP to respond to the UART or even to generate a GPIO interrupt that is recognized by the GIC400?

0 Hannan Khan over 8 years ago in reply to ran35366

Expert 1080 points

well i did try (and failed) to configure the GIC but as i said it lacks any real documentation so it might not be correct but here are the 2 methods i used

	    gCpuIntrf.gicDist = &distrIntrf;
	    gCpuIntrf.cpuIntfBasePtr = (void *)SOC_INTC_MPU_PHYS_CPU_IF_BASE;
	    distrIntrf.distBasePtr = (void *)SOC_INTC_MPU_DISTRIBUTOR_BASE;
	    gCpuIntrf.initStatus = (Uint32)FALSE;
	    gCpuIntrf.gicDist->initStatus = (Uint32)FALSE;
	    gCpuIntrf.pDefaultIntrHandlers = NULL;
	    gCpuIntrf.pDefaultUserParameter = NULL;

	    CSL_armGicInit(&gCpuIntrf);


	    cookie = HwiP_disable();

	    HwiP_Params_init(&hwiParams);

	    hwiParams.arg = NULL;
	    hwiParams.evtId = 152;
	    hwiParams.priority = 0x20;
	    hwiParams.triggerSensitivity = 0x3; /* interrupt edge triggered */
	    rxHwiHandle = HwiP_create(152, (HwiP_Fxn)&intIsr, &hwiParams);

	    HwiP_restore(cookie);

	a = 0;
	pinNum = 0;
	bankNum = 0;

	hGpio = CSL_GPIO_open (0);
	CSL_GPIO_setPinDirOutput (hGpio, pinNum);
    CSL_GPIO_setRisingEdgeDetect (hGpio, pinNum);
    CSL_GPIO_bankInterruptEnable (hGpio, bankNum);
    CSL_GPIO_clearOutputData (hGpio, pinNum);
    CSL_GPIO_getOutputData (hGpio, pinNum, &outData);
    CSL_GPIO_setOutputData (hGpio, pinNum);
    CSL_GPIO_getOutputData (hGpio, pinNum, &outData);

where the HwiP is located at ...ti/osal/src/nonos

and

	    gCpuIntrf.gicDist = &distrIntrf;
	    gCpuIntrf.cpuIntfBasePtr = (void *)SOC_INTC_MPU_PHYS_CPU_IF_BASE;
	    distrIntrf.distBasePtr = (void *)SOC_INTC_MPU_DISTRIBUTOR_BASE;
	    gCpuIntrf.initStatus = (Uint32)FALSE;
	    gCpuIntrf.gicDist->initStatus = (Uint32)FALSE;
	    gCpuIntrf.pDefaultIntrHandlers = NULL;
	    gCpuIntrf.pDefaultUserParameter = NULL;

	    CSL_armGicInit(&gCpuIntrf);

	gRtcIntrParams.triggerType = CSL_ARM_GIC_TRIG_TYPE_HIGH_LEVEL;
	gRtcIntrParams.priority = 0x20U;

    gRtcIntrParams.pFnIntrHandler = &intIsr;
    gRtcIntrParams.pUserParam = NULL;
    CSL_armGicEnableIntr(&gCpuIntrf, (CSL_ARM_GIC_GPIO_INT0 + 32));

    CSL_armGicConfigIntr(&gCpuIntrf, (CSL_ARM_GIC_GPIO_INT0 + 32), &gRtcIntrParams);



	a = 0;
	pinNum = 0;
	bankNum = 0;

	hGpio = CSL_GPIO_open (0);
	CSL_GPIO_setPinDirOutput (hGpio, pinNum);
    CSL_GPIO_setRisingEdgeDetect (hGpio, pinNum);
    CSL_GPIO_bankInterruptEnable (hGpio, bankNum);
    CSL_GPIO_clearOutputData (hGpio, pinNum);
    CSL_GPIO_getOutputData (hGpio, pinNum, &outData);
    CSL_GPIO_setOutputData (hGpio, pinNum);
    CSL_GPIO_getOutputData (hGpio, pinNum, &outData);

0 Hannan Khan over 8 years ago in reply to ran35366

Expert 1080 points

any update on this front?

0 ran35366 over 8 years ago in reply to Hannan Khan

TI__Genius 12805 points

Not yet. Engineering will release a fix in the future

0 Hannan Khan over 8 years ago in reply to ran35366

Expert 1080 points

Hello Ran !

okay so after working on interrupts for a bit and by using your tip that the issue might be in porting from the AM57 i was able to generate the interrupts to upto 279( didnt test above it). The problem to be honest was not that big all we need to do is to change the # of external interruot to 480 so that the fnRAMvector array etc are up to speed and then change the loop value which assigns MPU0 targets from 48 to 116U(this might need tweaking). also we need to mask out "r1 masking" in the ISR handler prolly which is in exception handler.s in my case
1 more thing is to increase the NUM_GICD_ENABLE REGS to 16U(dnt knw why but needed to be done)
i hope this helps others when using bare metal interrupts
let me know if any1 has any questions

regards !!
Hannan

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66AK2E05: Interrupts on ARM A15 noOS