AM3359: Slew rate of MDIO_CLK

reto hermann

Part Number: AM3359

Dear all,

we have a layout issue with the MDIO_CLK signal. The high slew rate of the IO driver is causing reflections and as a result of this some PHYs are detecting double clock edges. Is there a possibility to reduce the slew rate / drive strength of this IO pin (Pin M18, ZCZ package) by a register setting ?

Regards

Reto

over 8 years ago

0 Biser Gatchev-XID over 8 years ago

TI__Guru**** 393215 points

Hi,

You can try configuring the SLEWCTRL bit (bit 6) in pad control register CONF_MDC for slow mode (1b).

0 reto hermann over 8 years ago in reply to Biser Gatchev-XID

Intellectual 720 points

Hi,
thank you very much for your fast reply! Basically this helps, but the difference between the fast and the slow setting is very small.

Regards
Reto

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AM3359: Slew rate of MDIO_CLK