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RTOS/TMS320C6678: SRIO

dariush karami
Genius 3165 points

Part Number: TMS320C6678

Tool/software: TI-RTOS

Hi

My tools:

OS: Win 7

DSP: tms320c6678

Board: A  customized board with heterogeneous structure(FPGA and DSP)

In my scenario I want to send FPGA data from SRIO  to L2SRAM of DSP core and after processing the data, DSP return back data to FPGA from SRIO.

So I studied SRIO user guide document and investigated the examples in the PDK directory, Now I have some problems.

Question 1:

For my scenario I should use Direct I/O and LSU after set the RX.TX and port parameters.

Am I thinking right?

Question 2:

I didn't understand how to set the packets?(header,CRC,data....) Is there any example code?

Question 3:

I need that the size of data be dynamical( 100B ~ 1MB) so FPGA  send data in any size that need in a packet, Is it possible?

Best Regards

  • 0
    TI__Guru**** 161600 points
    Hi,

    I've notified the SRIO experts. Their feedback will be posted here.

    Best Regards,
    Yordan
  • 0
    TI__Mastermind 43296 points
    Hi Dariush,

    1. you can use Direct I/O or message passing to transfer data between DSP and FPGA.
    2. yes, multiple SRIO driver examples are available in PDK, see processors.wiki.ti.com/.../Processor_SDK_RTOS_SRIO.
    3. Maximum payload size of a SRIO packet is 256B. With Direct I/O, one SRIO transaction can support number of data bytes to Read/Write up to 1MB, see LSU_REG3 description.

    Regards,
    Garrett
  • 0 in reply to Garrett Ding
    Genius 3165 points

    Hi

    Thanks for your answers, I studied SPRUGW1B document and decided to use Direct I/O so I ran " C:\ti\pdk_C6678_1_1_2_6\packages\ti\drv\exampleProjects\SxRIO_LoopbackDioIsrexampleproject " example.

    The Demo works correct, next I investigate code and I have some questions.

    Q 1:

    How was calculated device ID and vendor ?(I copy and past the lines as below)

    const  uint32_t  DEVICE_ID1_16BIT = 0xBEEF;
    const  uint32_t  DEVICE_ID1_8BIT = 0xAB;
    const  uint32_t  DEVICE_ID2_16BIT = 0x4560;
    const  uint32_t  DEVICE_ID2_8BIT = 0xCD;
    const  uint32_t  DEVICE_ID3_16BIT = 0x1234;
    const  uint32_t  DEVICE_ID3_8BIT = 0x12;
    const  uint32_t  DEVICE_ID4_16BIT = 0x5678;
    const  uint32_t  DEVICE_ID4_8BIT = 0x56;

        CSL_SRIO_SetDeviceInfo (hSrio, DEVICE_ID1_16BIT, DEVICE_VENDOR_ID, DEVICE_REVISION);

    Q 2:

    What is the device ID and vendor about FPGA?

    Q 3:

    I couldn't find where set the size of pay load in the example, where is it?

    Q 4:

    I couldn't find where configure the path config  ports, where is it?

    Regards

  • 0 in reply to dariush karami
    TI__Mastermind 43296 points

    Hi dariush,


    1. See here for vendor ID: Device ID can be user defined.

    2. "SIZE_DIO_PACKET" is the payload size you can define, which need to be less than 256B. You probably need to update to latest PDK 2.x,

    3. This is done in SrioDevice_init, and default PATH_CONFIG 100 = Configuration 4 - 4 lanes, a maximum of 4 ports

    /* Configure the path mode for the ports. */
        for(i = 0; i < 4; i++)
            CSL_SRIO_SetPLMPortPathControlMode (hSrio, i, 0);

    Regards,

    Garrett