AISgen for OMAPL138

Hi,

I am also trying to bypass the UBL on the Zoom development kit and boot Uboot from AISGen, but I haven't had success yet either.

I have a question concerning the setup of the SDCR register:  This register has two different lock bits, "BOOTUNLOCK", and "TIMUNLOCK" which need to be set before changing certain fields in the SDCR.  I can see in the UBL code that these bits are unlocked before making changes exactly as the documentation describes, but does AISGen do the same?  It seems that AISGen relies on functions which are located in the OMAP's ROM area, so I can't verify exactly what happens when I set SDCR. 

I fear that if the lock bits are not set when writing to SDCR, the value read back from SDCR may not correspond to the actual state of the HW, is this the case?

Marc-Andre Hebert said:

I tried to use the settings I found in the UBL source but so far I am unable to boot.

Maybe you could share the settings you used?

Hi,

I took another shot at it, the results are a little better but still not perfect. When I use this configuration with the UART boot host, I can see that the bootloader is executed but the UART baud rate seems invalid (not the 115200 I am expecting). I say this because I can see the bootdelay countount keys being sent every second but the characters are all wrong, and if I press a key, I seem to access the u-boot prompt.

Here is the content of my .cfg file:

Boot Mode=UART2
Boot Speed=115200
Flash Width=0
Flash Timing=3ffffffc
Configure Peripheral=True
Configure PLL0=True
Configure SDRAM=False
Configure PLL1=True
Configure DDR2=True
Configure LPSC=False
Configure Pinmux=False
Enable CRC=False
Specify Entrypoint=False
Enable Sequential Read=False
Use 4.5 Clock Divider=False
Use DDR2 Direct Clock=False
Use mDDR=True
ROM ID=2
Device Type=0
Input Clock Speed=24
Clock Type=0
PLL0 Pre Divider=1
PLL0 Multiplier=25
PLL0 Post Divider=2
PLL0 Div1=1
PLL0 Div3=3
PLL0 Div7=6
PLL1 Multiplier=22
PLL1 Post Divider=2
PLL1 Div1=1
PLL1 Div2=2
PLL1 Div3=3
Entrypoint=0
SDRAM SDBCR=0
SDRAM SDTMR=0
SDRAM SDRSRPDEXIT=0
SDRAM SDRCR=0
DDR2 PHY=c4
DDR2 SDCR=a034622
DDR2 SDCR2=0
DDR2 SDTIMR=184929c8
DDR2 SDTIMR2=b80fc700
DDR2 SDRCR=406
LPSC0 Enable=
LPSC0 Disable=
LPSC0 SyncRst=
LPSC1 Enable=
LPSC1 Disable=
LPSC1 SyncRst=
Pinmux=
App File String=C:\projet\OMAPL138\u-boot-evm-uart
AIS File Name=C:\projet\OMAPL138\u-boot-evm-uart.ais

PD,

The AISGen setting for EMIF is supposed to comprehend the lock bits.

-Tommy