Hi,
I have questions about issues running U-boot on a custom-built board using Micron MT41K256M16TW-107 DDR3 and AM3358BZCZ100. After DDR3 Calibration, writing and reading DDR3 memory using CCS scripts worked well. However, using U-boot with the same DDR3 register values had hard time booting the board up to the U-boot prompt using a SD Card. U-boot was hung or went to re-setting in many cases. Writing memory seems ok at the U-boot prompt; but reading memory seems with issues. The SD card can boot a Beaglebone Black Board with no problem. I have attached the screen captures and EMIF0 register values for analyzing the issues. Thank you for anyone can help.
Best Regards,
CK Lui
Screen Captures:
CortxA8: Output: **** AM335x BeagleBlack Initialization is in progress ..........
CortxA8: Output: **** AM335x ALL PLL Config for OPP == OPP100 is in progress .........
CortxA8: Output: Input Clock Read from SYSBOOT[15:14]: 24MHz
CortxA8: Output: **** Going to Bypass...
CortxA8: Output: **** Bypassed, changing values...
CortxA8: Output: **** Locking ARM PLL
CortxA8: Output: **** Core Bypassed
CortxA8: Output: **** Now locking Core...
CortxA8: Output: **** Core locked
CortxA8: Output: **** DDR DPLL Bypassed
CortxA8: Output: **** DDR DPLL Locked
CortxA8: Output: **** PER DPLL Bypassed
CortxA8: Output: **** PER DPLL Locked
CortxA8: Output: **** DISP PLL Config is in progress ..........
CortxA8: Output: **** DISP PLL Config is DONE ..........
CortxA8: Output: **** AM335x ALL ADPLL Config for OPP == OPP100 is Done .........
CortxA8: Output: **** AM335x DDR3 EMIF and PHY configuration is in progress.........
CortxA8: Output: EMIF PRCM is in progress .......
CortxA8: Output: EMIF PRCM Done
CortxA8: Output: DDR PHY Configuration in progress
CortxA8: Output: Waiting for VTP Ready .......
CortxA8: Output: VTP is Ready!
CortxA8: Output: DDR PHY CMD0 Register configuration is in progress .......
CortxA8: Output: DDR PHY CMD1 Register configuration is in progress .......
CortxA8: Output: DDR PHY CMD2 Register configuration is in progress .......
CortxA8: Output: DDR PHY DATA0 Register configuration is in progress .......
CortxA8: Output: DDR PHY DATA1 Register configuration is in progress .......
CortxA8: Output: Setting IO control registers.......
CortxA8: Output: EMIF Timing register configuration is in progress .......
CortxA8: Output: EMIF Timing register configuration is done .......
CortxA8: Output: PHY is READY!!
CortxA8: Output: DDR PHY Configuration done
CortxA8: Output: **** AM335x BeagleBlack Initialization is Done ******************
CortxA8: GEL Output:
This EDMA test consists of 8 tests.
CortxA8: GEL Output: Write is completed Starting @0x80000000
CortxA8: GEL Output: Write is completed Starting @0x40300000
CortxA8: GEL Output:
Test 1
CortxA8: GEL Output: Write is completed Starting @0x80000000
CortxA8: GEL Output: EDMA Transfer Start for QUEPRI 0x00000000
CortxA8: GEL Output: EDMA Transfer Complete for QUEPRI 0x00000000
CortxA8: GEL Output: Test Case Passed for Destination Addr=0x40300000
CortxA8: GEL Output:
CortxA8: GEL Output: Write is completed Starting @0x40300800
CortxA8: GEL Output: EDMA Transfer Start for QUEPRI 0x00000000
CortxA8: GEL Output: EDMA Transfer Complete for QUEPRI 0x00000000
CortxA8: GEL Output: Test Case Passed for Destination Addr=0x80000800
CortxA8: GEL Output:
CortxA8: GEL Output:
Test 2
CortxA8: GEL Output: Write is completed Starting @0x80000000
CortxA8: GEL Output: EDMA Transfer Start for QUEPRI 0x00000001
CortxA8: GEL Output: EDMA Transfer Complete for QUEPRI 0x00000001
CortxA8: GEL Output: Test Case Passed for Destination Addr=0x40300000
CortxA8: GEL Output:
CortxA8: GEL Output: Write is completed Starting @0x40300800
CortxA8: GEL Output: EDMA Transfer Start for QUEPRI 0x00000001
CortxA8: GEL Output: EDMA Transfer Complete for QUEPRI 0x00000001
CortxA8: GEL Output: Test Case Passed for Destination Addr=0x80000800
CortxA8: GEL Output:
CortxA8: GEL Output:
Test 3
CortxA8: GEL Output: Write is completed Starting @0x80000000
CortxA8: GEL Output: EDMA Transfer Start for QUEPRI 0x00000002
CortxA8: GEL Output: EDMA Transfer Complete for QUEPRI 0x00000002
CortxA8: GEL Output: Test Case Passed for Destination Addr=0x40300000
CortxA8: GEL Output:
CortxA8: GEL Output: Write is completed Starting @0x40300800
CortxA8: GEL Output: EDMA Transfer Start for QUEPRI 0x00000002
CortxA8: GEL Output: EDMA Transfer Complete for QUEPRI 0x00000002
CortxA8: GEL Output: Test Case Passed for Destination Addr=0x80000800
CortxA8: GEL Output:
CortxA8: GEL Output:
Test 4
CortxA8: GEL Output: Write is completed Starting @0x80000000
CortxA8: GEL Output: EDMA Transfer Start for QUEPRI 0x00000003
CortxA8: GEL Output: EDMA Transfer Complete for QUEPRI 0x00000003
CortxA8: GEL Output: Test Case Passed for Destination Addr=0x40300000
CortxA8: GEL Output:
CortxA8: GEL Output: Write is completed Starting @0x40300800
CortxA8: GEL Output: EDMA Transfer Start for QUEPRI 0x00000003
CortxA8: GEL Output: EDMA Transfer Complete for QUEPRI 0x00000003
CortxA8: GEL Output: Test Case Passed for Destination Addr=0x80000800
CortxA8: GEL Output:
CortxA8: GEL Output:
Test 5
CortxA8: GEL Output: Write is completed Starting @0x80000000
CortxA8: GEL Output: EDMA Transfer Start for QUEPRI 0x00000004
CortxA8: GEL Output: EDMA Transfer Complete for QUEPRI 0x00000004
CortxA8: GEL Output: Test Case Passed for Destination Addr=0x40300000
CortxA8: GEL Output:
CortxA8: GEL Output: Write is completed Starting @0x40300800
CortxA8: GEL Output: EDMA Transfer Start for QUEPRI 0x00000004
CortxA8: GEL Output: EDMA Transfer Complete for QUEPRI 0x00000004
CortxA8: GEL Output: Test Case Passed for Destination Addr=0x80000800
CortxA8: GEL Output:
CortxA8: GEL Output:
Test 6
CortxA8: GEL Output: Write is completed Starting @0x80000000
CortxA8: GEL Output: EDMA Transfer Start for QUEPRI 0x00000005
CortxA8: GEL Output: EDMA Transfer Complete for QUEPRI 0x00000005
CortxA8: GEL Output: Test Case Passed for Destination Addr=0x40300000
CortxA8: GEL Output:
CortxA8: GEL Output: Write is completed Starting @0x40300800
CortxA8: GEL Output: EDMA Transfer Start for QUEPRI 0x00000005
CortxA8: GEL Output: EDMA Transfer Complete for QUEPRI 0x00000005
CortxA8: GEL Output: Test Case Passed for Destination Addr=0x80000800
CortxA8: GEL Output:
CortxA8: GEL Output:
Test 7
CortxA8: GEL Output: Write is completed Starting @0x80000000
CortxA8: GEL Output: EDMA Transfer Start for QUEPRI 0x00000006
CortxA8: GEL Output: EDMA Transfer Complete for QUEPRI 0x00000006
CortxA8: GEL Output: Test Case Passed for Destination Addr=0x40300000
CortxA8: GEL Output:
CortxA8: GEL Output: Write is completed Starting @0x40300800
CortxA8: GEL Output: EDMA Transfer Start for QUEPRI 0x00000006
CortxA8: GEL Output: EDMA Transfer Complete for QUEPRI 0x00000006
CortxA8: GEL Output: Test Case Passed for Destination Addr=0x80000800
CortxA8: GEL Output:
CortxA8: GEL Output:
Test 8
CortxA8: GEL Output: Write is completed Starting @0x80000000
CortxA8: GEL Output: EDMA Transfer Start for QUEPRI 0x00000007
CortxA8: GEL Output: EDMA Transfer Complete for QUEPRI 0x00000007
CortxA8: GEL Output: Test Case Passed for Destination Addr=0x40300000
CortxA8: GEL Output:
CortxA8: GEL Output: Write is completed Starting @0x40300800
CortxA8: GEL Output: EDMA Transfer Start for QUEPRI 0x00000007
CortxA8: GEL Output: EDMA Transfer Complete for QUEPRI 0x00000007
CortxA8: GEL Output: Test Case Passed for Destination Addr=0x80000800
CortxA8: GEL Output:
CortxA8: GEL Output: Test is complete
---------------------------
EMIF0 EMIF0 Configuration Registers
EMIF_MOD_ID_REV 0x40443403 Memory Mapped
STATUS 0x40000004 Memory Mapped
SDRAM_CONFIG 0x61C05332 Memory Mapped
SDRAM_CONFIG_2 0x00000000 Memory Mapped
SDRAM_REF_CTRL 0x00000C30 Memory Mapped
SDRAM_REF_CTRL_SHDW 0x00000C30 Memory Mapped
SDRAM_TIM_1 0x199DFB1B Memory Mapped
SDRAM_TIM_1_SHDW 0x199DFB1B Memory Mapped
SDRAM_TIM_2 0x26047FDA Memory Mapped
SDRAM_TIM_2_SHDW 0x26047FDA Memory Mapped
SDRAM_TIM_3 0x501F866F Memory Mapped
SDRAM_TIM_3_SHDW 0x501F866F Memory Mapped
PWR_MGMT_CTRL 0x00000000 Memory Mapped
PWR_MGMT_CTRL_SHDW 0x00000000 Memory Mapped
INT_CONFIG 0x00FFFFFF Memory Mapped
INT_CFG_VAL_1 0x8000140A Memory Mapped
INT_CFG_VAL_2 0x00021616 [Memory Mapped]
PERF_CNT_1 0x01D2316B Memory Mapped
PERF_CNT_2 0x0008A8C1 Memory Mapped
PERF_CNT_CFG 0x00010000 Memory Mapped
PERF_CNT_SEL 0x00000000 Memory Mapped
PERF_CNT_TIM 0x78495A2F Memory Mapped
READ_IDLE_CTRL 0x00050000 Memory Mapped
READ_IDLE_CTRL_SHDW 0x00050000 Memory Mapped
IRQSTATUS_RAW_SYS 0x00000000 Memory Mapped
IRQSTATUS_SYS 0x00000000 Memory Mapped
IRQENABLE_SET_SYS 0x00000000 Memory Mapped
IRQENABLE_CLR_SYS 0x00000000 Memory Mapped
ZQ_CONFIG 0x50074BE4 Memory Mapped
RDWR_LVL_RMP_WIN 0x00000000 [Memory Mapped]
RDWR_LVL_RMP_CTRL 0x00000000 Memory Mapped
RDWR_LVL_CTRL 0x00000000 Read-Write Leveling Control Register [Memory Mapped]
DDR_PHY_CTRL_1 0x00000007 A write to the DDR PHY Control 1 register must be followed by a write to the SDRAM_CONFIG register to ensure that the control update/acknowledge protocol is performed on the DID. If CAS latency = 5, the minimum read latency = 5 + 2 = 7 and reg_read_latency must be programmed as 7 - 1 = 6. The maximum read latency = 5 + 7 = 12 and reg_read_latency must be programmed as 12 - 1 = 11. [Memory Mapped]
DDR_PHY_CTRL_1_SHDW 0x00000007 A write to the DDR PHY Control 1 register must be followed by a write to the SDRAM_CONFIG register to ensure that the control update/acknowledge protocol is performed on the DID. If CAS latency = 5, the minimum read latency = 5 + 2 = 7 and reg_read_latency must be programmed as 7 - 1 = 6. The maximum read latency = 5 + 7 = 12 and reg_read_latency must be programmed as 12 - 1 = 11. [Memory Mapped]
PRI_COS_MAP 0x00000000 Memory Mapped
CONNID_COS_1_MAP 0x00000000 Memory Mapped
CONNID_COS_2_MAP 0x00000000 [Memory Mapped]
RD_WR_EXEC_THRSH 0x00000305 Memory Mapped
---------------------------
EMIF0 EMIF0 Configuration Registers
EMIF_MOD_ID_REV 0x40443403
STATUS 0x40000004
SDRAM_CONFIG 0x61C05332
SDRAM_CONFIG_2 0x00000000
SDRAM_REF_CTRL 0x00000C30
SDRAM_REF_CTRL_SHDW 0x00000C30
SDRAM_TIM_1 0x0AAAD4DB
SDRAM_TIM_1_SHDW 0x0AAAD4DB
SDRAM_TIM_2 0x466B7FDA
SDRAM_TIM_2_SHDW 0x466B7FDA
SDRAM_TIM_3 0x501F861F
SDRAM_TIM_3_SHDW 0x501F861F
PWR_MGMT_CTRL 0x00000000
PWR_MGMT_CTRL_SHDW 0x00000000
INT_CONFIG 0x00FFFFFF
INT_CFG_VAL_1 0x8000140A
INT_CFG_VAL_2 0x00021616
PERF_CNT_1 0x01D2316B
PERF_CNT_2 0x0008A8C1
PERF_CNT_CFG 0x00010000
PERF_CNT_SEL 0x00000000
PERF_CNT_TIM 0x818244AB
READ_IDLE_CTRL 0x00050000
READ_IDLE_CTRL_SHDW 0x00050000
IRQSTATUS_RAW_SYS 0x00000000
IRQSTATUS_SYS 0x00000000
IRQENABLE_SET_SYS 0x00000000
IRQENABLE_CLR_SYS 0x00000000
====================================================
U-Boot SPL 2016.11-rc3-dirty (Jan 09 2017 - 12:04:45)
spl_board_init.
Reading EEPROM.
Start PMIC configuration.
bone_lt from EPROM.
Trying to boot from MMC1
Config spl_os_boot.
Config spl_en_support.
reading u-boot.img
reading u-boot.img
U-Boot 2016.11-rc3-dirty (Jan 09 2017 - 12:04:45 -0800)
CPU : AM335X-GP rev 2.1
I2C: ready
DRAM: 512 MiB
Start board initialization.
Boot Parameters initialization.
cpsw initialization.
MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
Using default environment
---------------------------
U-Boot SPL 2016.11-rc3-dirty (Jan 09 2017 - 12:04:45)
spl_board_init.
Reading EEPROM.
Start PMIC configuration.
bone_lt from EPROM.
Trying to boot from MMC1
Config spl_os_boot.
Config spl_en_support.
reading u-boot.img
reading u-boot.img
U-Boot 2016.11-rc3-dirty (Jan 09 2017 - 12:04:45 -0800)
CPU : AM335X-GP rev 2.1
I2C: ready
DRAM: 512 MiB
Start board initialization.
Boot Parameters initialization.
cpsw initialization.
MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
Using default environment
late init.
Reading EEPROM.
read eeprom.
Set to BBG1
Net: Ethernet validating
<ethaddr> not set. Validating first E-fuse MAC
Reading EEPROM.
cpsw
Press SPACE to abort autoboot in 2 seconds
=> md 4c000000
4c000000: 40443403 40000004 61c05332 00000000 .4D@...@2S.a....
4c000010: 00000c30 00000c30 0aaad4db 0aaad4db 0...0...........
4c000020: 466b7fda 466b7fda 501f861f 501f861f ..kF..kF...P...P
4c000030: 00000000 00000000 00000000 00000000 ................
4c000040: 00000000 00000000 00000000 00000000 ................
4c000050: 00000000 00ffffff 8000140a 00021616
---------------------------
U-Boot SPL 2016.11-rc3-dirty (Jan 09 2017 - 12:04:45)
spl_board_init.
Reading EEPROM.
Start PMIC configuration.
bone_lt from EPROM.
Trying to boot from MMC1
Config spl_os_boot.
Config spl_en_support.
reading u-boot.img
reading u-boot.img
U-Boot 2016.11-rc3-dirty (Jan 09 2017 - 12:04:45 -0800)
CPU : AM335X-GP rev 2.1
I2C: ready
DRAM: 512 MiB
Start board initialization.
Boot Parameters initialization.
cpsw initialization.
MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
Using default environment
late init.
Reading EEPROM.
read eeprom.
Set to BBG1
Net: Ethernet validating
<ethaddr> not set. Validating first E-fuse MAC
Reading EEPROM.
cpsw
Press SPACE to abort autoboot in 2 seconds
=> md 4c000000
4c000000: 40443403 40000004 61c05332 00000000 .4D@...@2S.a....
4c000010: 00000c30 00000c30 0aaad4db 0aaad4db 0...0...........
4c000020: 466b7fda 466b7fda 501f861f 501f861f ..kF..kF...P...P
4c000030: 00000000data abort
---------------------------
U-Boot SPL 2016.11-rc3-dirty (Jan 09 2017 - 12:04:45)
spl_board_init.
Reading EEPROM.
Start PMIC configuration.
bone_lt from EPROM.
Trying to boot from MMC1
Config spl_os_boot.
Config spl_en_support.
reading u-boot.img
reading u-boot.img
U-Boot 2016.11-rc3-dirty (Jan 09 2017 - 12:04:45 -0800)
CPU : AM335X-GP rev 2.1
I2C: ready
DRAM: 512 MiB
Start board initialization.
Boot Parameters initialization.
cpsw initialization.
MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
Using default environment
late init.
Reading EEPROM.
read eeprom.
Set to BBG1
Net: Ethernet validating
<ethaddr> not set. Validating first E-fuse MAC
prefetch abort
pc : [<1ff86fc4>] lr : [<9ff86fa1>]
reloc pc : [<00834fc4>] lr : [<80834fa1>]
sp : 9df31d88 ip : 00000062 fp : 00000000
r10: ffffffff r9 : 9df31ed8 r8 : 9df31dda
r7 : ffffffff r6 : fffffffe r5 : 00000002 r4 : 9df31e3c
r3 : 00000034 r2 : 00000020 r1 : 9df31dd7 r0 : 00000011
Flags: Nzcv IRQs off FIQs on Mode SVC_32
Resetting CPU ...
resetting ...
---------------------------
U-Boot SPL 2016.11-rc3-dirty (Jan 09 2017 - 12:04:45)
spl_board_init.
Reading EEPROM.
Start PMIC configuration.
bone_lt from EPROM.
Trying to boot from MMC1
Config spl_os_boot.
Config spl_en_support.
reading u-boot.img
reading u-boot.img
U-Boot 2016.11-rc3-dirty (Jan 09 2017 - 12:04:45 -0800)
CPU : AM335X-GP rev 2.1
I2C: ready
DRAM: 512 MiB
Start board initialization.
Boot Parameters initialization.
cpsw initialization.
MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
Using default environment
late init.
Reading EEPROM.
read eeprom.
Set to BBG1
Net: Ethernet validating
<ethaddr> not set. Validating first E-fuse MAC
Reading EEPROM.
cpsw
Press SPACE to abort autoboot in 2 seconds
=> help mw
mw - memory write (fill)
Usage:
mw [.b, .w, .l] address value [count]
=> mw 0x88000000 0xAFAFAFAF 0x1000
=> md 0x88000000
88000000: afafafaf afafafaf afafafaf afafafaf ................
88000010:prefetch abort
pc : [<1ff8728e>] lr : [<9ff871bd>]
reloc pc : [<0083528e>] lr : [<808351bd>]
sp : 9df319b0 ip : 0000000f fp : 00000008
r10: 00000000 r9 : 9df31ed8 r8 : 00000010
r7 : 9df31cc8 r6 : ffffffff r5 : 00000021 r4 : 9df31abb
r3 : 00000001 r2 : 9df31ab5 r1 : 00000066 r0 : 00000030
Flags: nzCv IRQs off FIQs on Mode SVC_32
Resetting CPU ...
resetting ...
---------------------------
EMIF0 EMIF0 Configuration Registers
EMIF_MOD_ID_REV 0x40443403
STATUS 0x40000004
SDRAM_CONFIG 0x61C05332
SDRAM_CONFIG_2 0x00000000
SDRAM_REF_CTRL 0x00000C30
SDRAM_REF_CTRL_SHDW 0x00000C30
SDRAM_TIM_1 0x0AAAD4DB
SDRAM_TIM_1_SHDW 0x0AAAD4DB
SDRAM_TIM_2 0x466B7FDA
SDRAM_TIM_2_SHDW 0x466B7FDA
SDRAM_TIM_3 0x501F861F
SDRAM_TIM_3_SHDW 0x501F861F
PWR_MGMT_CTRL 0x00000000
PWR_MGMT_CTRL_SHDW 0x00000000
INT_CONFIG 0x00FFFFFF
INT_CFG_VAL_1 0x8000140A
INT_CFG_VAL_2 0x00021616
PERF_CNT_1 0x004730F5
PERF_CNT_2 0x00014672
PERF_CNT_CFG 0x00010000
PERF_CNT_SEL 0x00000000
PERF_CNT_TIM 0x03D5AC72
READ_IDLE_CTRL 0x00050000
READ_IDLE_CTRL_SHDW 0x00050000
IRQSTATUS_RAW_SYS 0x00000000
IRQSTATUS_SYS 0x00000000
IRQENABLE_SET_SYS 0x00000000
IRQENABLE_CLR_SYS 0x00000000
ZQ_CONFIG 0x50074BE4
RDWR_LVL_RMP_WIN 0x00000000
RDWR_LVL_RMP_CTRL 0x00000000
RDWR_LVL_CTRL 0x00000000
DDR_PHY_CTRL_1 0x00000007
DDR_PHY_CTRL_1_SHDW 0x00000007
PRI_COS_MAP 0x00000000
CONNID_COS_1_MAP 0x00000000
CONNID_COS_2_MAP 0x00000000
RD_WR_EXEC_THRSH 0x00000305
| EMIF0 | EMIF0 Configuration Registers | |
| EMIF_MOD_ID_REV | 0x40443403 | |
| STATUS | 0x40000004 | |
| SDRAM_CONFIG | 0x61C05332 | |
| SDRAM_CONFIG_2 | 0x00000000 | |
| SDRAM_REF_CTRL | 0x00000C30 | |
| SDRAM_REF_CTRL_SHDW | 0x00000C30 | |
| SDRAM_TIM_1 | 0x0AAAD4DB | |
| SDRAM_TIM_1_SHDW | 0x0AAAD4DB | |
| SDRAM_TIM_2 | 0x466B7FDA | |
| SDRAM_TIM_2_SHDW | 0x466B7FDA | |
| SDRAM_TIM_3 | 0x501F861F | |
| SDRAM_TIM_3_SHDW | 0x501F861F | |
| PWR_MGMT_CTRL | 0x00000000 | |
| PWR_MGMT_CTRL_SHDW | 0x00000000 | |
| INT_CONFIG | 0x00FFFFFF | |
| INT_CFG_VAL_1 | 0x8000140A | |
| INT_CFG_VAL_2 | 0x00021616 | |
| PERF_CNT_1 | 0x01D2316B | |
| PERF_CNT_2 | 0x0008A8C1 | |
| PERF_CNT_CFG | 0x00010000 | |
| PERF_CNT_SEL | 0x00000000 | |
| PERF_CNT_TIM | 0x818244AB | |
| READ_IDLE_CTRL | 0x00050000 | |
| READ_IDLE_CTRL_SHDW | 0x00050000 | |
| IRQSTATUS_RAW_SYS | 0x00000000 | |
| IRQSTATUS_SYS | 0x00000000 | |
| IRQENABLE_SET_SYS | 0x00000000 | |
| IRQENABLE_CLR_SYS | 0x00000000 |
