Device Held at Reset - When trying to connect IPU1_M4 in DRA7x

jeyaseelan kirubaharan

Other Parts Discussed in Thread: DRA72

Hi ,

I am trying to connect IPU-1 M4 from debugger of CCS while DRA72x already running a standalone code from flash (Both A15 and M4).When i do so, i am getting "Not able to connect to the Target -Cortex M4 , Device held at reset " error from the startup_M4.gel script of debugger.

Is it possible to connect and load new program through the debugger while processor is executing a standalone code?

I have tried to put clock and reset(wakeup) initialization of IPU1, with PRCM_BASE and WAKE_UP register base from OnTargetConnect() function of DRA72x_cortexM4_startup.gel scrpt. The error occured even before this function is called from start up gel script.

These gel files are for Vayu board.My current target is based on dra7xx evm.Are there any differences in gel files for both of them. JTAG looks fine and it passes the test connection test from debugger.

I have attached the screen shots also for reference.

With regards,

Jeyaseelan

Fullscreen Clock_Reset_Snippet_in_Startup_Cortex_M4_Gel_Script.txt Download

#define WR_MEM_32(addr, data)   *(unsigned int*)(addr) =(unsigned int)(data)

DRA72x_ICEPickD_Utility.gel

#define DRA72x_PRCM_BASE       0x4A005000
#define CM_IPU1_CLK_CTRL       0x500
#define CM_IPU1_IPU1_CLKCTRL   0x520
#define RM_IPU1_RST_CTRL       0x4AE06510
#define RM_IPU1_RSTSTS         0x4AE06514

#define WR_MEM_32(addr, data)   *(unsigned int*)(addr) =(unsigned int)(data)


		   /*------------------ Reset-IPU1 -------------------*/
   WR_MEM_32(DRA72x_PRCM_BASE+CM_IPU1_CLK_CTRL,0x2);
   WR_MEM_32(CM_IPU1_IPU1_CLKCTRL,0x01000001);
   WR_MEM_32(RM_IPU1_RST_CTRL,0x7);	
   
   Console Output :
   
   Cortex_M4_IPU1_C0: GEL Output: --->>> DRA72x Cortex M4 Startup Sequence In Progress... <<<---
Cortex_M4_IPU1_C0: GEL Output: --->>> DRA72x Cortex M4 Startup Sequence DONE! <<<---
Cortex_M4_IPU1_C1: GEL Output: --->>> DRA72x Cortex M4 Startup Sequence In Progress... <<<---
Cortex_M4_IPU1_C1: GEL Output: --->>> DRA72x Cortex M4 Startup Sequence DONE! <<<---
Cortex_M4_IPU2_C0: GEL Output: --->>> DRA72x Cortex M4 Startup Sequence In Progress... <<<---
Cortex_M4_IPU2_C0: GEL Output: --->>> DRA72x Cortex M4 Startup Sequence DONE! <<<---
Cortex_M4_IPU2_C1: GEL Output: --->>> DRA72x Cortex M4 Startup Sequence In Progress... <<<---
Cortex_M4_IPU2_C1: GEL Output: --->>> DRA72x Cortex M4 Startup Sequence DONE! <<<---
C66xx_DSP1: GEL Output: --->>> DRA72x C66x DSP Startup Sequence In Progress... <<<---
C66xx_DSP1: GEL Output: --->>> DRA72x C66x DSP Startup Sequence DONE! <<<---
CortexA15_0: GEL Output: --->>> DRA72x Cortex A15 Startup Sequence In Progress... <<<---
CortexA15_0: GEL Output: --->>> DRA72x Cortex A15 Startup Sequence DONE! <<<---
IcePick_D: GEL Output: Ipu RTOS is released from Wait-In-Reset. 
IcePick_D: GEL Output: Ipu SIMCOP is released from Wait-In-Reset. 
IcePick_D: GEL Output: IVAHD C66 is released from Wait-In-Reset. 
IcePick_D: GEL Output: IVAHD ICONT1 is released from Wait-In-Reset. 
IcePick_D: GEL Output: IVAHD ICONT2 is released from Wait-In-Reset. 
Cortex_M4_IPU1_C0: Error connecting to the target: (Error -1266 @ 0x0) Device is held in reset. Take the device out of reset, and retry the operation. (Emulation package 6.0.14.5)

over 8 years ago

0 jeyaseelan kirubaharan over 8 years ago

Expert 1330 points

When tried to connect A15 first,getting the following console output from debugger.

Cortex_M4_IPU1_C0: GEL Output: --->>> DRA72x Cortex M4 Startup Sequence In Progress... <<<---
Cortex_M4_IPU1_C0: GEL Output: --->>> DRA72x Cortex M4 Startup Sequence DONE! <<<---
Cortex_M4_IPU1_C1: GEL Output: --->>> DRA72x Cortex M4 Startup Sequence In Progress... <<<---
Cortex_M4_IPU1_C1: GEL Output: --->>> DRA72x Cortex M4 Startup Sequence DONE! <<<---
Cortex_M4_IPU2_C0: GEL Output: --->>> DRA72x Cortex M4 Startup Sequence In Progress... <<<---
Cortex_M4_IPU2_C0: GEL Output: --->>> DRA72x Cortex M4 Startup Sequence DONE! <<<---
Cortex_M4_IPU2_C1: GEL Output: --->>> DRA72x Cortex M4 Startup Sequence In Progress... <<<---
Cortex_M4_IPU2_C1: GEL Output: --->>> DRA72x Cortex M4 Startup Sequence DONE! <<<---
C66xx_DSP1: GEL Output: --->>> DRA72x C66x DSP Startup Sequence In Progress... <<<---
C66xx_DSP1: GEL Output: --->>> DRA72x C66x DSP Startup Sequence DONE! <<<---
CortexA15_0: GEL Output: --->>> DRA72x Cortex A15 Startup Sequence In Progress... <<<---
CortexA15_0: GEL Output: --->>> DRA72x Cortex A15 Startup Sequence DONE! <<<---
IcePick_D: GEL Output: Perform an ICEPick System Reset.
IcePick_D: GEL Output: Ipu RTOS is released from Wait-In-Reset.
IcePick_D: GEL Output: Ipu SIMCOP is released from Wait-In-Reset.
IcePick_D: GEL Output: IVAHD C66 is released from Wait-In-Reset.
IcePick_D: GEL Output: IVAHD ICONT1 is released from Wait-In-Reset.
IcePick_D: GEL Output: IVAHD ICONT2 is released from Wait-In-Reset.
CS_DAP_DebugSS: GEL Output: --->>> CONFIGURE DEBUG DPLL settings to 1.9 GHZs <<<---
CS_DAP_DebugSS: GEL Output: > Setup DebugSS 1.9GHz in progress...
CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS Trace export clock (TPIU) to 97MHz
CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS PLL Clocking 1.9GHz
CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS ATB Clocking 380MHz
CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS Trace export clock (TPIU) to 97MHz
CS_DAP_DebugSS: GEL Output: --->>> TURNING ON L3_INSTR and L3_3 clocks required for debug instrumention <<<<<<----
CS_DAP_DebugSS: GEL Output: ---<<< L3 instrumentation clocks are enabled >>>> ---
CS_DAP_DebugSS: GEL Output: --->>> Mapping TIMER supsend sources to default cores <<<<<<----
CS_DAP_PC: GEL Output: Cortex-A15 1 is not in WIR mode so nothing to do.
CortexA15_0: GEL Output: --->>> DRA72x Target Connect Sequence Begins ... <<<---
CortexA15_0: GEL: Error while executing OnTargetConnect(): Target failed to read memory at 0x4A002204 at (*((unsigned int *) 0x4A002204)&0xF0000000) [DRA72x_startup_common.gel:127] at DRA72x_show_device_info()

[DRA72x_startup_common.gel:104] at DRA72x_target_connect_sequence() [DRA72x_startup_common.gel:40] at OnTargetConnect() .
CortexA15_0: GEL Output: --->>> IPU1SS Initialization is in progress ... <<<---
DRA72x_MULTICORE_EnableAllCores() cannot be evaluated.
target is not connected
at *((unsigned int *) ((cpu_num==1) ? (((0x4AE00000+0x6000)+0x500)+0x10) : (((0x4AE00000+0x6000)+0x700)+0x210)))=(unsigned int) 0x7 [DRA72x_multicore_reset.gel:12]
at IPUSSClkEnable(1) [DRA72x_multicore_reset.gel:196]
at IPU1SSClkEnable_API() [DRA72x_multicore_reset.gel:170]
at DRA72x_MULTICORE_EnableAllCores()

0 Karl Wallinger over 8 years ago in reply to jeyaseelan kirubaharan

TI__Genius 16410 points

Hello Jeyaseelan,

Let me move this to the DRAx forum, they should be able to answer your question.

Regards,
Karl

0 jeyaseelan kirubaharan over 8 years ago in reply to Karl Wallinger

Expert 1330 points

Sure Karl.Please post it in the right forum.Thanks !!!

With regards,

Jeyaseelan

0 Prasad Jondhale over 8 years ago in reply to jeyaseelan kirubaharan

TI__Mastermind 27743 points

Hello Jeyaseelan,

Ideally you should run gel files from DRA75x_DRA74x directory, though i guess you should be able to enable IPU1 with DRA72 gel.

In your gel log i dont see you enabling IPU1 core. Can you please run DRA72x_MULTICORE_EnableAllCores function through scripts menu ?The function is defined in DRA72x_multicore_reset.gel

Please share gel logs if any issues.

0 Alex Bashkov over 8 years ago

TI__Genius 13550 points

Jeyaseelan,

Let's get the A15 error out the way first. I think you will be able to get IPU rolling after this no problem.

For DRA72x lets use precisely the DRA72x device support. Latest automotive device support(v1.0.4) is available thought the update site on the TI cloud ( ) or the offline package here

. If you are using the offline installer go to the <CCS install dir>\ccsv6\ folder and paste the downloaded files over to replace/update everything and Restart CCS.

Reset your board.
Create DRA72x target config, save and test make sure it passes.
Launch a new debug session on the freshly created target configuration.

You should now see the following log(without errors):

Cortex_M4_IPU1_C0: GEL Output: --->>> DRA72x Cortex M4 Startup Sequence In Progress... <<<---
Cortex_M4_IPU1_C0: GEL Output: --->>> DRA72x Cortex M4 Startup Sequence DONE! <<<---
Cortex_M4_IPU1_C1: GEL Output: --->>> DRA72x Cortex M4 Startup Sequence In Progress... <<<---
Cortex_M4_IPU1_C1: GEL Output: --->>> DRA72x Cortex M4 Startup Sequence DONE! <<<---
Cortex_M4_IPU2_C0: GEL Output: --->>> DRA72x Cortex M4 Startup Sequence In Progress... <<<---
Cortex_M4_IPU2_C0: GEL Output: --->>> DRA72x Cortex M4 Startup Sequence DONE! <<<---
Cortex_M4_IPU2_C1: GEL Output: --->>> DRA72x Cortex M4 Startup Sequence In Progress... <<<---
Cortex_M4_IPU2_C1: GEL Output: --->>> DRA72x Cortex M4 Startup Sequence DONE! <<<---
C66xx_DSP1: GEL Output: --->>> DRA72x C66x DSP Startup Sequence In Progress... <<<---
C66xx_DSP1: GEL Output: --->>> DRA72x C66x DSP Startup Sequence DONE! <<<---
CortexA15_0: GEL Output: --->>> DRA72x Cortex A15 Startup Sequence In Progress... <<<---
CortexA15_0: GEL Output: --->>> DRA72x Cortex A15 Startup Sequence DONE! <<<---

4. Connect to CortexA15_0

You should now see the following log(without errors):

IcePick_D: GEL Output: Ipu RTOS is released from Wait-In-Reset. 
IcePick_D: GEL Output: Ipu SIMCOP is released from Wait-In-Reset. 
IcePick_D: GEL Output: IVAHD C66 is released from Wait-In-Reset. 
IcePick_D: GEL Output: IVAHD ICONT1 is released from Wait-In-Reset. 
IcePick_D: GEL Output: IVAHD ICONT2 is released from Wait-In-Reset. 
CS_DAP_DebugSS: GEL Output: --->>> CONFIGURE DEBUG DPLL settings to 1.9 GHZs  <<<---
CS_DAP_DebugSS: GEL Output: > Setup DebugSS 1.9GHz in progress...
CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS Trace export clock (TPIU) to 97MHz 
CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS PLL Clocking 1.9GHz 
CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS ATB Clocking 380MHz 
CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS Trace export clock (TPIU) to 97MHz 
CS_DAP_DebugSS: GEL Output: --->>> TURNING ON L3_INSTR and L3_3 clocks required for debug instrumention <<<<<<----
CS_DAP_DebugSS: GEL Output: ---<<< L3 instrumentation clocks are enabled >>>> ---
CS_DAP_DebugSS: GEL Output: --->>> Mapping TIMER supsend sources to default cores <<<<<<----
CS_DAP_PC: GEL Output: Cortex-A15 1 is not in WIR mode so nothing to do.
CortexA15_0: GEL Output: --->>> DRA72x Target Connect Sequence Begins ... <<<---
CortexA15_0: GEL Output: 	--->>> DRA72x PG2.0 GP device <<<---
CortexA15_0: GEL Output: 	--->>> The core is in non-SECURE state. <<<---
CortexA15_0: GEL Output: --->>> PRCM Clock Configuration for OPPNOM in progress... <<<---
CortexA15_0: GEL Output: 	Cortex A15 DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	Cortex A15 DPLL is already locked, now unlocking...  
CortexA15_0: GEL Output: 	Cortex A15 DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	IVA DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	IVA DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	PER DPLL OPP 0 clock config in progress...
CortexA15_0: GEL Output: 	PER DPLL already locked, now unlocking  
CortexA15_0: GEL Output: 	PER DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	CORE DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	CORE DPLL OPP  already locked, now unlocking....  
CortexA15_0: GEL Output: 	CORE DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	ABE DPLL OPP 0 clock config in progress...
CortexA15_0: GEL Output: 	ABE DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	GMAC DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	GMAC DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	GPU DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	GPU DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	DSP DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	DSP DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: 	PCIE_REF DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: 	PCIE_REF DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: --->>> PRCM Clock Configuration for OPP 0 is DONE! <<<---
CortexA15_0: GEL Output: --->>> PRCM Configuration for all modules in progress... <<<---
CortexA15_0: GEL Output: --->>> PRCM Configuration for all modules is DONE! <<<---
CortexA15_0: GEL Output: --->>> DDR3 Initialization is in progress ... <<<---
CortexA15_0: GEL Output: 	DDR DPLL clock config for 666MHz is in progress...
CortexA15_0: GEL Output: 	DDR DPLL clock config for 666MHz is in DONE!
CortexA15_0: GEL Output:        Launch full leveling
CortexA15_0: GEL Output:        Updating slave ratios in PHY_STATUSx registers
CortexA15_0: GEL Output:        as per HW leveling output
CortexA15_0: GEL Output:        HW leveling is now disabled. Using slave ratios from 
CortexA15_0: GEL Output:        PHY_STATUSx registers
CortexA15_0: GEL Output: --->>> DDR3 Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> DRA72x Target Connect Sequence DONE !!!!!  <<<---

Note the other cores are still held in reset. So connected(and suspended) while at the CortexA15_0 selection

5. Go to Scripts>DRA72x PRCM MODULE Configuraion>DRA72x_PRCM_module_AllEnable_Confi

6. Go to Scripts>DRA72x MULTICORE Initialization>DRA72x_MULTICORE_EnableAllCores

You should now see the following log(without errors):

CortexA15_0: GEL Output: --->>> IPU1SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: --->>> IPU1SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> IPU2SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: --->>> IPU2SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> DSP1SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: DEBUG: Clock is active ... 
CortexA15_0: GEL Output: DEBUG: Checking for data integrity in DSPSS L2RAM ... 
CortexA15_0: GEL Output: DEBUG: Data integrity check in GEM L2RAM is sucessful! 
CortexA15_0: GEL Output: --->>> DSP1SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> IVAHD Initialization is in progress ... <<<---
CortexA15_0: GEL Output: DEBUG: Clock is active ... 
CortexA15_0: GEL Output: --->>> IVAHD Initialization is DONE! ... <<<---
CortexA15_0: GEL Output: --->>> PRUSS 1 and 2 Initialization is in progress ... <<<---
CortexA15_0: GEL Output: --->>> PRUSS 1 and 2 Initialization is in complete ... <<<---

If you haven't receive any errors yet, try connecting to the IPU now it should work fine. Let us know the results.

Thanks

Alex

0 jeyaseelan kirubaharan over 8 years ago in reply to Alex Bashkov

Expert 1330 points

Hi Alex/Prasad,

Manually starting the debugger from Target configuration file from target configuration window (user defined) works to some extent(here not able to step through the code though code looks running). But auto loading the out file from project window by right clicking target config file and select Debug As option ->code composer studio results in error

Actually, first i changed the sysboot dip switches to change the default ROM Monitor setting to boot from UART mode, to prevent A15 to automatically start executing code from Flash before connecting the debugger.After that i launched manually, the target configuration file from target configuration window ,which opened the debugger correctly.Then i just followed the steps what Alex has mentioned,connected A15 target first,run the DRA72x_MULTICORE_EnableAllCores.gel file,then connected the IPU1 target,Loaded an out file manually.IPU1 showed running green icon.(I assume the code is running here ). I 'm just assuming as, source code window is not loaded into the debugger and not breaks at main().My question here is how to see the source code in the debugger so that i can step through them(while it is running in IPU1) .

I have attached the gel output in both (manual and auto ) scenarios in the below attachments. Kindly let me know how to step through the .c files code using debugger and why there is an error during auto loading .out file from project window.

Thanks.

With regards,
Jeyaseelan

0 jeyaseelan kirubaharan over 8 years ago in reply to jeyaseelan kirubaharan

Expert 1330 points

Manual Load Log

Cortex_M4_IPU1_C0: GEL Output: --->>> DRA72x Cortex M4 Startup Sequence In Progress... <<<---
Cortex_M4_IPU1_C0: GEL Output: --->>> DRA72x Cortex M4 Startup Sequence DONE! <<<---
Cortex_M4_IPU1_C1: GEL Output: --->>> DRA72x Cortex M4 Startup Sequence In Progress... <<<---
Cortex_M4_IPU1_C1: GEL Output: --->>> DRA72x Cortex M4 Startup Sequence DONE! <<<---
Cortex_M4_IPU2_C0: GEL Output: --->>> DRA72x Cortex M4 Startup Sequence In Progress... <<<---
Cortex_M4_IPU2_C0: GEL Output: --->>> DRA72x Cortex M4 Startup Sequence DONE! <<<---
Cortex_M4_IPU2_C1: GEL Output: --->>> DRA72x Cortex M4 Startup Sequence In Progress... <<<---
Cortex_M4_IPU2_C1: GEL Output: --->>> DRA72x Cortex M4 Startup Sequence DONE! <<<---
C66xx_DSP1: GEL Output: --->>> DRA72x C66x DSP Startup Sequence In Progress... <<<---
C66xx_DSP1: GEL Output: --->>> DRA72x C66x DSP Startup Sequence DONE! <<<---
CortexA15_0: GEL Output: --->>> DRA72x Cortex A15 Startup Sequence In Progress... <<<---
CortexA15_0: GEL Output: --->>> DRA72x Cortex A15 Startup Sequence DONE! <<<---
IcePick_D: GEL Output: Perform an ICEPick System Reset.
IcePick_D: GEL Output: Ipu RTOS is released from Wait-In-Reset.
IcePick_D: GEL Output: Ipu SIMCOP is released from Wait-In-Reset.
IcePick_D: GEL Output: IVAHD C66 is released from Wait-In-Reset.
IcePick_D: GEL Output: IVAHD ICONT1 is released from Wait-In-Reset.
IcePick_D: GEL Output: IVAHD ICONT2 is released from Wait-In-Reset.
CS_DAP_DebugSS: GEL Output: --->>> CONFIGURE DEBUG DPLL settings to 1.9 GHZs <<<---
CS_DAP_DebugSS: GEL Output: > Setup DebugSS 1.9GHz in progress...
CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS Trace export clock (TPIU) to 97MHz
CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS PLL Clocking 1.9GHz
CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS ATB Clocking 380MHz
CS_DAP_DebugSS: GEL Output: < Done with Setup DebugSS Trace export clock (TPIU) to 97MHz
CS_DAP_DebugSS: GEL Output: --->>> TURNING ON L3_INSTR and L3_3 clocks required for debug instrumention <<<<<<----
CS_DAP_DebugSS: GEL Output: ---<<< L3 instrumentation clocks are enabled >>>> ---
CS_DAP_DebugSS: GEL Output: --->>> Mapping TIMER supsend sources to default cores <<<<<<----
CS_DAP_PC: GEL Output: Cortex-A15 1 is not in WIR mode so nothing to do.
CortexA15_0: GEL Output: --->>> DRA72x Target Connect Sequence Begins ... <<<---
CortexA15_0: GEL Output: --->>> DRA72x PG1.0 GP device <<<---
CortexA15_0: GEL Output: --->>> The core is in non-SECURE state. <<<---
CortexA15_0: GEL Output: --->>> PRCM Clock Configuration for OPPNOM in progress... <<<---
CortexA15_0: GEL Output: Cortex A15 DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: Cortex A15 DPLL is already locked, now unlocking...
CortexA15_0: GEL Output: Cortex A15 DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: IVA DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: IVA DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: PER DPLL OPP 0 clock config in progress...
CortexA15_0: GEL Output: PER DPLL already locked, now unlocking
CortexA15_0: GEL Output: PER DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: CORE DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: CORE DPLL OPP already locked, now unlocking....
CortexA15_0: GEL Output: CORE DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: ABE DPLL OPP 0 clock config in progress...
CortexA15_0: GEL Output: ABE DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: GMAC DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: GMAC DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: GPU DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: GPU DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: DSP DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: DSP DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: PCIE_REF DPLL OPP 0 clock config is in progress...
CortexA15_0: GEL Output: PCIE_REF DPLL OPP 0 is DONE!
CortexA15_0: GEL Output: --->>> PRCM Clock Configuration for OPP 0 is DONE! <<<---
CortexA15_0: GEL Output: --->>> PRCM Configuration for all modules in progress... <<<---
CortexA15_0: GEL Output: --->>> PRCM Configuration for all modules is DONE! <<<---
CortexA15_0: GEL Output: --->>> DDR3 Initialization is in progress ... <<<---
CortexA15_0: GEL Output: DDR DPLL clock config for 666MHz is in progress...
CortexA15_0: GEL Output: DDR DPLL clock config for 666MHz is in DONE!
CortexA15_0: GEL Output: Launch full leveling
CortexA15_0: GEL Output: ERROR: HW-Leveling time-out
CortexA15_0: GEL Output: --->>> DDR3 Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> DRA72x Target Connect Sequence DONE !!!!! <<<---
CortexA15_0: GEL Output: --->>> IPU1SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: --->>> IPU1SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> IPU2SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: --->>> IPU2SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> DSP1SS Initialization is in progress ... <<<---
CortexA15_0: GEL Output: DEBUG: Clock is active ...
CortexA15_0: GEL Output: DEBUG: Checking for data integrity in DSPSS L2RAM ...
CortexA15_0: GEL Output: DEBUG: Data integrity check in GEM L2RAM is sucessful!
CortexA15_0: GEL Output: --->>> DSP1SS Initialization is DONE! <<<---
CortexA15_0: GEL Output: --->>> IVAHD Initialization is in progress ... <<<---
CortexA15_0: GEL Output: DEBUG: Clock is active ...
CortexA15_0: GEL Output: --->>> IVAHD Initialization is DONE! ... <<<---
CortexA15_0: GEL Output: --->>> PRUSS 1 and 2 Initialization is in progress ... <<<---
CortexA15_0: GEL Output: --->>> PRUSS 1 and 2 Initialization is in complete ... <<<---

0 jeyaseelan kirubaharan over 8 years ago in reply to jeyaseelan kirubaharan

Expert 1330 points

Auto Load Error Log :

Cortex_M4_IPU1_C0: GEL Output: --->>> DRA72x Cortex M4 Startup Sequence In Progress... <<<---
Cortex_M4_IPU1_C0: GEL Output: --->>> DRA72x Cortex M4 Startup Sequence DONE! <<<---
Cortex_M4_IPU1_C1: GEL Output: --->>> DRA72x Cortex M4 Startup Sequence In Progress... <<<---
Cortex_M4_IPU1_C1: GEL Output: --->>> DRA72x Cortex M4 Startup Sequence DONE! <<<---
Cortex_M4_IPU2_C0: GEL Output: --->>> DRA72x Cortex M4 Startup Sequence In Progress... <<<---
Cortex_M4_IPU2_C0: GEL Output: --->>> DRA72x Cortex M4 Startup Sequence DONE! <<<---
Cortex_M4_IPU2_C1: GEL Output: --->>> DRA72x Cortex M4 Startup Sequence In Progress... <<<---
Cortex_M4_IPU2_C1: GEL Output: --->>> DRA72x Cortex M4 Startup Sequence DONE! <<<---
C66xx_DSP1: GEL Output: --->>> DRA72x C66x DSP Startup Sequence In Progress... <<<---
C66xx_DSP1: GEL Output: --->>> DRA72x C66x DSP Startup Sequence DONE! <<<---
CortexA15_0: GEL Output: --->>> DRA72x Cortex A15 Startup Sequence In Progress... <<<---
CortexA15_0: GEL Output: --->>> DRA72x Cortex A15 Startup Sequence DONE! <<<---
IcePick_D: GEL Output: Perform an ICEPick System Reset.
IcePick_D: GEL Output: Ipu RTOS is released from Wait-In-Reset.
IcePick_D: GEL Output: Ipu SIMCOP is released from Wait-In-Reset.
IcePick_D: GEL Output: IVAHD C66 is released from Wait-In-Reset.
IcePick_D: GEL Output: IVAHD ICONT1 is released from Wait-In-Reset.
IcePick_D: GEL Output: IVAHD ICONT2 is released from Wait-In-Reset.
ARM9_ICONT1: Error connecting to the target: (Error -2062 @ 0x34BC) Unable to halt device. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 6.0.14.5)

0 Alex Bashkov over 8 years ago in reply to jeyaseelan kirubaharan

TI__Genius 13550 points

Hi Jeyaseelan,

jeyaseelan kirubaharan said:
Actually, first i changed the sysboot dip switches to change the default ROM Monitor setting to boot from UART mode, to prevent A15 to automatically start executing code from Flash before connecting the debugger.

So that was violating the gel execution in your initial issue. Thanks for letting us know!

jeyaseelan kirubaharan said:
I 'm just assuming as, source code window is not loaded into the debugger and not breaks at main().My question here is how to see the source code in the debugger so that i can step through them(while it is running in IPU1) .

I have attached the gel output in both (manual and auto ) scenarios in the below attachments. Kindly let me know how to step through the .c files code using debugger and why there is an error during auto loading .out file from project window.

That looks like Code composer general GUI issue not opening up project to to step through. Please ping the experts over at the CCS forum here:

Let us know if we can close this particular thread as the original issue is resolved.

Thanks

Alex

0 jeyaseelan kirubaharan over 8 years ago in reply to Alex Bashkov

Expert 1330 points

Thanks Alex.This thread can be closed .I will post the question related to debugger in the appropriate forum.

Processors

Processors forum

Device Held at Reset - When trying to connect IPU1_M4 in DRA7x