I have an issue concerning the OMAPL-137 and the McASP usage with DMA.
When I fill in the buffer to be transmit and I start the DMA, the first 4 active slots are good , then the next 4 active slots are bad , then the next 4 active slots are good and etc...
For example:
Tx_dma_src = [ 0x82; 0x00 ;0xFC ; 0x28; 0x82; 0x00 ;0xFC ; 0x28; 0x82; 0x00 ;0xFC ; 0x28; etc....... ] ( size is 2*bcnt for ping pong. )
But when we check data on the receive side or in the middle with the scope, we see : [ 0x28; 0x82; 0x00 ;0xFC ; 0x28; 0x28; 0x00 ;0x00 ; 0x28 0x82; 0x00 ;0xFC ; 0x28; 0x28; 0x00 ;0x00 etc....... ]
So I may understand the shift because the first event is generated on a sync for the slot 1 ( is it ? ), but I don't know why one sequence out of two is bad as we never stop the dma and our ASYNC transfert is not finished...
Here is a brief description of our setup:
- We use McASP in TDM mode with 32 slots.
- External clock is connected to AHCLKR1
- Clock is generated on ACLKR1 and ACLKR1 is linked to ACLKX1.
- Sync is generated on AFSR1 and AFSR1 is linked to AFSX1
- AHCLKX1 is used as a gpio
- AXR1[0] is our receive serialiser
- AXR1[1] is our transmit serialiser.
On the 32 slots we only use the first 4 slots ( 0,1,2,3) .
We have followed the initialization sequence in the datasheet SPRUGB8, paragraph 2.4.1.2, with DMA.
So actually when we start DMA and put out of reset the McASP we have got ( verified with an oscilloscope).
- 2048Mhz clock on ACLKR1 ( and so ACLKX1 )
- A frame sync every 32 slots on AFSR1 ( and so AFSX1 ). ( long sync of 8 bits ).
- Tx and Rx data are stable on falling edge.
- Fifo is enabled , MSB first, no padding, data width 8 bits..
Note: in this configuration we want to use SYNC mode for RX and Tx but i think we cannot because clock is connected to AHCLKR1 and generated on ACLKR1, and to use SYNC mode we need ACLKX1 to generate the clock.
We have configured 2 DMA one for Rx and one for Tx. They are registered with channel 2 and 3 and so, each event corresponds to a request for data in an active slot.
DMA configuration is:
acnt = 1 ; --> we transmit one byte per active slot.
bnct = 4 * 80; --> we want to transmit 80 chunk with 4 slots
ccnt = 1;
ASYNC transfert
DMA buffer are static for omapl137, Tx_dma_dest = 0x1d06200 for Tx and Rx_dma_source = 0x1d06000; ( we use two different address in the memory area to avoid confusion ).
DMA interrupts on transfert complete.
We use DAM for the transmit DMA and SAM for the received DMA.
We used ping pong mode for DMA
PS: here is a small dump of the main register for McASP ( All values are in HEX ):
GPFUNC = a000ffc
PDIR = a2000002
GLBCTL = 1f1f
RXGLB = 1f1f
RxMask = ff
RxFmt = 8036
AFSRCTL = 1012
ACLKRCTL = 2b
ASP AHCLKRCTL = 0
RXTDM = f
RxTDMslot = 12
RxStat = 154
RxCLKcheck = c2000000
TxGlb = 1f1f
TxMask = ff000000
TxFMT = 8030
AFSXCTL = 1010
ACLKXCTL = 40
AHCLKXCTL = 8000
TxTDM = f
TxTDMSlot = 12
TxClkcheck = 0
SRCTL0 = 2
SRCTL1 = 11
WFIFOCTR = 10101
RFIFOCTR = 10101
And for the DMA ( ParamSET struct):
Transmit DMA
EDMA: opt= [80103002] -src= [c2a350a0] -a_b_cnt= [a00001] -dst= [1d06200] -src_dst_bidx= [1] -link_bcntrldc= [740] -src_dst_cidx= [0] -ccnt= [1]
Ping EDMA: opt= [80103002] -src= [c2a35140] -a_b_cnt= [1400001] -dst= [1d06200] -src_dst_bidx= [1] -link_bcntrldc= [760] -src_dst_cidx= [0] -ccnt= [1]
Pong EDMA: opt= [80103002] -src= [c2a35000] -a_b_cnt= [1400001] -dst= [1d06200] -src_dst_bidx= [1] -link_bcntrldc= [740] -src_dst_cidx= [0] -ccnt= [1]
Receive DMA:
EDMA: opt= [80102001] -src= [1d06000] -a_b_cnt= [e00001] -dst= [c2cf81a0] -src_dst_bidx= [10000] -link_bcntrldc= [720] -src_dst_cidx= [10000] -ccnt= [1]
Ping EDMA: opt= [80102001] -src= [1d06000] -a_b_cnt= [1400001] -dst= [c2cf8140] -src_dst_bidx= [10000] -link_bcntrldc= [720] -src_dst_cidx= [10000] -ccnt= [1]
Pong EDMA: opt= [80102001] -src= [1d06000] -a_b_cnt= [1400001] -dst= [c2cf8000] -src_dst_bidx= [10000] -link_bcntrldc= [700] -src_dst_cidx= [10000] -ccnt= [1]
Teodor
