• State TI Thinks Resolved
  • Locked Locked
  • Replies 2 replies
  • Answers 1 answer
  • Subscribers 99 subscribers
  • Views 387 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

XEVMK2EX: Use of K2E reserved pins test points.

Tarang Jindal68
Intellectual 820 points

Part Number: XEVMK2EX

Hello, 

There are multiple reserved pins in the K2E SoC. These pins are connected to test points. 

I noted that, there are three types of test points used for reserved pins. Also some reserved pins are directly connected to test point and some are through 0E Res. 

Why these test points are provided on reserved pins and why there is a mismatch between test point type and why some have 0E res and some do not have.

According to K2E SoC, these reserved pins should be NC, can we left these pins NC?

Thanks and Regards

Tarang Jindal

 

  • 0
    TI__Guru 65405 points
    Hi Tarang,

    I've forwarded this to the design team. Their feedback should be posted here.

    BR
    Tsvetolin Shulev
  • 0 in reply to Cvetolin Shulev-XID
    TI__Mastermind 46460 points

    Tarang,

    Reserved pins are used during silicon validation, manufacturing and testing.  These reserved pins are also sometimes used during prototype EVM design and validation.  These are not functional pins for customer use.  Normally they are "Not Connected" on customer boards but sometimes they need to be biased to a certain level.  In all cases, the required connections and or bias levels are listed in the Data Manual.  You must follow the guidance in the Data Manual.  There is no need for your board to have the test points or the resistors shown in the EVM schematic.

    Tom