Linux: U-boot SPL bootloading problem with AM571x

Hi Ganesh,

One of the main differences between AM572x and AM571x devices is that AM571x has only one EMIF controller, thus fewer DDR memoy can be used. Can you check from which memory region exactly this malloc function is trying to get bytes and if you really have this memory mapped on the EMIF controller.

Also the internal RAM (OCMC RAM) is different, 512KB for AM571x and 2.5MB for AM572x. You can also check if that malloc is trying to get bytes from OCMC RAM.

See the below doc:

www.ti.com/.../sprabx8c.pdf

Regards,
Pavel

Hi Pavel,

The malloc function is trying to get bytes from DDR. Before mmc_init function, DDR is getting initialized and after during memory test whatever data are written to DDR is not matching with reading back data. So it is considering memory size as zero. It was unable to allocate memory. Actually, I am also using the same DDR ICs used in the AM572x EVM, but memory test fails.


Best Regards,
Ganesh

Ganesh,

Thanks for confirming that your DDR is not right.

Regards,

Pavel

Hi Pavel,

Any suggestions for debugging DDR problem?

Best Regards,
Ganesh

Ganesh Tenka said:

Actually, I am also using the same DDR ICs used in the AM572x EVM, but memory test fails.

Which memory test you are using? Have you tried with u-boot test below?

u-boot/doc/README.memory-test
u-boot/common/memsize.c

AM572x has two EMIF controllers, 2GByte total. What is your AM571x board DDR size?

You should check how J6Eco/DRA72x EVM is designed regarding DDR3. J6Eco has single EMIF with 4x 4Gbit 8-bit chips, MT41K512M8RH-125, 2GByte total RAM.

You can also check how AM571x IDK is designed regarding DDR3. IDK has single EMIF with 2x 4Gbit 16-bit chips, MT41K256M16HA-125, 1GByte total RAM.

See also the below pointers:

Regards,
Pavel

Hi Pavel,


I am using the same test in memsize.c, simply writing and reading data. I am using AM571x processor. EMIF with 512MD DDRs(KINGSTON make used in AM572x EVM). 1GB total memory. While performing the test i am getting the below results with 3 boards,

Board1:
Expected value = fffffffe and Read Value = 2c000000
Expected value = fffffffd and Read Value = 20000000
Expected value = fffffffb and Read Value = 2c000000
Expected value = fffffff7 and Read Value = 2c000000
Expected value = ffffffef and Read Value = 2c000000
Expected value = ffffffdf and Read Value = 2c000000
Expected value = ffffffbf and Read Value = 2c000000
Expected value = ffffff7f and Read Value = 2c000000
Expected value = fffffeff and Read Value = 2c000000
Expected value = fffffdff and Read Value = 20000000
Expected value = fffffbff and Read Value = 2c000000
Expected value = fffff7ff and Read Value = 2c000000
Expected value = ffffefff and Read Value = 2c000000
Expected value = ffffdfff and Read Value = 20000000
Expected value = ffffbfff and Read Value = 2c000000
Expected value = ffff7fff and Read Value = 2c000000
Expected value = fffeffff and Read Value = 28000000
Expected value = fffdffff and Read Value = 28000000
Expected value = fffbffff and Read Value = 28000000
Expected value = fff7ffff and Read Value = 2c000000
Expected value = ffefffff and Read Value = 0
Expected value = ffdfffff and Read Value = 2c000000
Expected value = ffbfffff and Read Value = 2c000000
Expected value = ff7fffff and Read Value = 20000000
Expected value = feffffff and Read Value = 20000000
Expected value = fdffffff and Read Value = 2c000000
Expected value = fbffffff and Read Value = 2c000000
Expected value = f7ffffff and Read Value = 2c000000

Expected value = 1 and Read Value = 0
Expected value = 2 and Read Value = 2c000000
Expected value = 4 and Read Value = 28000000
Expected value = 8 and Read Value = 2c000000
Expected value = 10 and Read Value = 2c000000
Expected value = 20 and Read Value = 20000000
Expected value = 40 and Read Value = 0
Expected value = 80 and Read Value = 2c000000
Expected value = 100 and Read Value = 20000000
Expected value = 200 and Read Value = 20000000
Expected value = 400 and Read Value = 2c000000
Expected value = 800 and Read Value = 0
Expected value = 1000 and Read Value = 2c000000
Expected value = 2000 and Read Value = 0
Expected value = 4000 and Read Value = 20000000
Expected value = 8000 and Read Value = 20000000
Expected value = 10000 and Read Value = 20000000
Expected value = 20000 and Read Value = 20000000
Expected value = 40000 and Read Value = 2c000000
Expected value = 80000 and Read Value = 20000000
Expected value = 100000 and Read Value = 2c000000
Expected value = 200000 and Read Value = 20000000
Expected value = 400000 and Read Value = 2c000000
Expected value = 800000 and Read Value = 2c000000
Expected value = 1000000 and Read Value = 0
Expected value = 2000000 and Read Value = 2c000000
Expected value = 4000000 and Read Value = 20000000
Expected value = 8000000 and Read Value = 20000000

Board2:

Expected value = fffffffe and Read Value = fd
Expected value = fffffffd and Read Value = bb0008
Expected value = fffffffb and Read Value = bb00fd
Expected value = fffffff7 and Read Value = bb003c
Expected value = ffffffef and Read Value = bb0008
Expected value = ffffffdf and Read Value = bb0000
Expected value = ffffffbf and Read Value = bb0000
Expected value = ffffff7f and Read Value = bb003c
Expected value = fffffeff and Read Value = bb003c
Expected value = fffffdff and Read Value = b3003c
Expected value = fffffbff and Read Value = bb003c
Expected value = fffff7ff and Read Value = b30008
Expected value = ffffefff and Read Value = bb003c
Expected value = ffffdfff and Read Value = b3003c
Expected value = ffffbfff and Read Value = bb003c
Expected value = ffff7fff and Read Value = b3003c
Expected value = fffeffff and Read Value = b3003c
Expected value = fffdffff and Read Value = b3003c
Expected value = fffbffff and Read Value = b3003c
Expected value = fff7ffff and Read Value = b3003c
Expected value = ffefffff and Read Value = bb003c
Expected value = ffdfffff and Read Value = bb003c
Expected value = ffbfffff and Read Value = b3003c
Expected value = ff7fffff and Read Value = b3003c
Expected value = feffffff and Read Value = bb003c
Expected value = fdffffff and Read Value = b30008
Expected value = fbffffff and Read Value = b3003c
Expected value = f7ffffff and Read Value = bb0008
Expected value = 1 and Read Value = 1c
Expected value = 2 and Read Value = bb003c
Expected value = 4 and Read Value = bb001c
Expected value = 8 and Read Value = b30008
Expected value = 10 and Read Value = bb001c
Expected value = 20 and Read Value = b3001c
Expected value = 40 and Read Value = bb0000
Expected value = 80 and Read Value = bb001c
Expected value = 100 and Read Value = bb0000
Expected value = 200 and Read Value = bb0000
Expected value = 400 and Read Value = b30000
Expected value = 800 and Read Value = bb0000
Expected value = 1000 and Read Value = bb0000
Expected value = 2000 and Read Value = bb0008
Expected value = 4000 and Read Value = b30000
Expected value = 8000 and Read Value = b30008
Expected value = 10000 and Read Value = bb0008
Expected value = 20000 and Read Value = bb001c
Expected value = 40000 and Read Value = b30008
Expected value = 80000 and Read Value = bb001c
Expected value = 100000 and Read Value = b30008
Expected value = 200000 and Read Value = bb001c
Expected value = 400000 and Read Value = bb0008
Expected value = 800000 and Read Value = b30000
Expected value = 1000000 and Read Value = b30008
Expected value = 2000000 and Read Value = bb0000
Expected value = 4000000 and Read Value = bb001c
Expected value = 8000000 and Read Value = bb0000

Board3:

Expected value = fffffffe and Read Value = 0
Expected value = fffffffd and Read Value = 869a
Expected value = fffffffb and Read Value = 829a
Expected value = fffffff7 and Read Value = 829a
Expected value = ffffffef and Read Value = 869a
Expected value = ffffffdf and Read Value = 829a
Expected value = ffffffbf and Read Value = 8298
Expected value = ffffff7f and Read Value = 829a
Expected value = fffffeff and Read Value = 829a
Expected value = fffffdff and Read Value = 829a
Expected value = fffffbff and Read Value = 829a
Expected value = fffff7ff and Read Value = 829a
Expected value = ffffefff and Read Value = 829a
Expected value = ffffdfff and Read Value = 829a
Expected value = ffffbfff and Read Value = 829a
Expected value = ffff7fff and Read Value = 829a
Expected value = fffeffff and Read Value = 829a
Expected value = fffdffff and Read Value = 829a
Expected value = fffbffff and Read Value = 829a
Expected value = fff7ffff and Read Value = 829a
Expected value = ffefffff and Read Value = 829a
Expected value = ffdfffff and Read Value = 829a
Expected value = ffbfffff and Read Value = 829a
Expected value = ff7fffff and Read Value = 829a
Expected value = feffffff and Read Value = 829a
Expected value = fdffffff and Read Value = 829a
Expected value = fbffffff and Read Value = 829a
Expected value = f7ffffff and Read Value = 829a
Expected value = 1 and Read Value = 0
Expected value = 2 and Read Value = 829a
Expected value = 4 and Read Value = 869a
Expected value = 8 and Read Value = 829a
Expected value = 10 and Read Value = 829a
Expected value = 20 and Read Value = 829a
Expected value = 40 and Read Value = 829a
Expected value = 80 and Read Value = 829a
Expected value = 100 and Read Value = 829a
Expected value = 200 and Read Value = 829a
Expected value = 400 and Read Value = 829a
Expected value = 800 and Read Value = 829a
Expected value = 1000 and Read Value = 829a
Expected value = 2000 and Read Value = 829a
Expected value = 4000 and Read Value = 829a
Expected value = 8000 and Read Value = 829a
Expected value = 10000 and Read Value = 829a
Expected value = 20000 and Read Value = 829a
Expected value = 40000 and Read Value = 829a
Expected value = 80000 and Read Value = 829a
Expected value = 100000 and Read Value = 829a
Expected value = 200000 and Read Value = 829a
Expected value = 400000 and Read Value = 8298
Expected value = 800000 and Read Value = 829a
Expected value = 1000000 and Read Value = 829a
Expected value = 2000000 and Read Value = 829a
Expected value = 4000000 and Read Value = 829a
Expected value = 8000000 and Read Value = 829a

Is it any timing issues or layout??

Best Regards,
Ganesh

Ganesh,

It is hard to say for sure but looks like layout issue. At which DDR3 frequency you are running the test? Can you try with the lowest freq possible?

Can you provide the lisa_map registers values?

Regards,
Pavel

Pavel,

At which DDR3 frequency you are running the test?
532MHz


Can you provide the lisa_map registers values?
.dmm_lisa_map_3 = 0x80640100,
.is_ma_present = 0x1
Also SDRAM config register values:
.sdram_config_init = 0x61851AB2,
.sdram_config = 0x61851AB2,
.sdram_config2 = 0x00000000,
.ref_ctrl = 0x000040F1,
.ref_ctrl_final = 0x00001035,
.sdram_tim1 = 0xCCCF365B,
.sdram_tim2 = 0x305A7FDA,
.sdram_tim3 = 0x407F8558,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x5007190b,
.temp_alert_config = 0x00000000,
.emif_ddr_phy_ctlr_1_init = 0x0024400b,
.emif_ddr_phy_ctlr_1 = 0x0e24400b,
.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
.emif_ddr_ext_phy_ctrl_2 = 0x00820082,
.emif_ddr_ext_phy_ctrl_3 = 0x008b008b,
.emif_ddr_ext_phy_ctrl_4 = 0x00800080,
.emif_ddr_ext_phy_ctrl_5 = 0x007e007e,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
.emif_rd_wr_exec_thresh = 0x00000305

The processor I am using is AM5718 and I am using CS0 of DDR1 and the chip select selection bit of SDRAM config register is 0 only.


Best Regards,
Ganesh.

DMM_LISA_MAP settings seems correct.

Can you try with lower frequency, like 303MHz for example?

From what I understand you are using 1GByte RAM, 2x 512MByte DDR3 chips attached on EMIF1. No ECC? What DDR3 chips exactly you are using? On the AM571x IDK there are two MT41K256M16HA-125 chips.

See also if the below wiki pages will be in help:
processors.wiki.ti.com/.../AM571x_Power_Estimation_Tool
processors.wiki.ti.com/.../AM57xx_Schematic_Checklist
processors.wiki.ti.com/.../Processor_SDK_RTOS_FAQ

Regards,
Pavel

Pavel,

You are correct that 1GByte RAM, 2x 512MByte DDR3 chips attached on EMIF1 and no ECC. I am using Kingston D2516EC4BXGGB DDR chips.

-------------------------------------------------------------------------------------------

Can you try with lower frequency, like 303MHz for example?

-------------------------------------------------------------------------------------------

I am not aware of changing DDR frequency in u-boot. Do we need to modify only emif_regs for changing DDR Frequency ?

Best Regards,

Ganesh

Ganesh,

AM572x EVM use the same Kingston DDR chips - D2516EC4BXGGB. The only difference is that AM572x has two EMIFs, EMIF1 and EMIF2, and has 1GByte (2 Kingston DDR chips) on EMIF1 and 1GByte (2 Kingston DDR chips) on EMIF2.

processors.wiki.ti.com/.../AM572x_General_Purpose_EVM_HW_User_Guide

So I would suggest you to re-use the settings from the AM572x EVM. Just note that you should disable EMIF2. You can see how this is done (EMIF2 not used) for the AM571x IDK.

Regards,
Pavel

You can also see how the GEL file is initializing DDR3 chips:

ccsv6/ccs_base/emulation/boards/am572x/gel/AM572x_emif_macros.gel
ccsv6/ccs_base/emulation/boards/am572x/gel/AM572x_ddr_config.gel

There is macro IS_EMIF2_AVAILABLE, you can use it to see how to program EMIF1 only. See also the below e2e thread:

e2e.ti.com/.../559412

You can also check how AM571x IDK DDR3 chips are programmed:

ccsv6/ccs_base/emulation/boards/am571x/gel/AM571x_emif_macros.gel
ccsv6/ccs_base/emulation/boards/am571x/gel/AM571x_ddr_config.gel

Regards,
Pavel