Hi
I am using a C6472 rapid IO CSL to communicate with an Altera FPGA via SRIO. The code I am running is posted on Altera's website
http://www.altera.com/support/refdesigns/ip/interface/ref-serial-rapidio-to-ti-6482-dsp.html
What I'm having an issue with is getting the link to transfer data AFTER I reload the DSP. I think the issue is related to ACKIDs. Below is the output after a power-on reset of the DSP.
INFO : Link IS UP!
Start srio_write
srio_write completed
SP_ERR_STAT (0x2d01158) = 0x2
: b1 - io port OK.
LSU0_REG6 (0x2d00418) = 0x0
b4-b1 = 0
: transaction complete.
SP_LM_RESP (0x2d01144) = 0x80000010
ACKID_STATUS = 0x0, LINK_STATUS = 0x10
SP_ACKID_STAT (0x2d01148) = 0x100
ACKIDS: INBOUND = 0x0, OUTSTANDING = 0x1, OUTBOUND = 0x0
Start srio_read
SP_ERR_STAT (0x2d01158) = 0x2
: b1 - io port OK.
LSU0_REG6 (0x2d00418) = 0x0
b4-b1 = 0
: transaction complete.
SRIO readback data matched send data. Sent 0xbeef0000, rxvd 0xbeef0000
SP_LM_RESP (0x2d01144) = 0x10
ACKID_STATUS = 0x0, LINK_STATUS = 0x10
SP_ACKID_STAT (0x2d01148) = 0x1000200
ACKIDS: INBOUND = 0x1, OUTSTANDING = 0x2, OUTBOUND = 0x0
Note that the inbound and outstanding ACKIDs are increasing as expected.
But after doing a DSP code reload, there are no INBOUND ACKIDs (it stays zero) and the write and reads fail.
INFO : Link IS UP!
Start srio_write
srio_write completed
SP_ERR_STAT (0x2d01158) = 0x2
: b1 - io port OK.
LSU0_REG6 (0x2d00418) = 0x0
b4-b1 = 0
: transaction complete.
SP_LM_RESP (0x2d01144) = 0x80000010
ACKID_STATUS = 0x0, LINK_STATUS = 0x10
SP_ACKID_STAT (0x2d01148) = 0x100
ACKIDS: INBOUND = 0x0, OUTSTANDING = 0x1, OUTBOUND = 0x0
Start srio_read
SP_ERR_STAT (0x2d01158) = 0x2
: b1 - io port OK.
LSU0_REG6 (0x2d00418) = 0x2
b4-b1 = 1
: timeout occured on non-posted transaction.
SRIO readback data DID NOT match. Sent 0xbeef0000, rxvd 0x0
SP_LM_RESP (0x2d01144) = 0x10
ACKID_STATUS = 0x0, LINK_STATUS = 0x10
SP_ACKID_STAT (0x2d01148) = 0x200
ACKIDS: INBOUND = 0x0, OUTSTANDING = 0x2, OUTBOUND = 0x0
Note that the read failed, inbound is zero and the outstanding is 2. As the code tries the second transfer, inbound stays at zero and outstanding increases to 3, and so on. So it appears the FPGA is not sending ACKIDs. And although it said the write transaction is completed, the FPGA did not get written to.
From these results I conclude that there is something in the hard DSP reset that gets the FPGA SRIO link running (I am not resetting or changing any registers in the FPGA).
I have discovered that if I do this sequence, I can successfully reload the DSP without a hard reset:
- Stop the DSP
- Do a DSP system reset
- Toggle the PORT_DIS bit in the FPGA 0x15c (Port Control CSR) register. (this causes a force_reinit in the FPGA SRIO core)
- Reload DSP and then run.
I've read the SRIO guide sprue13h.pdf Appendix A which I don't think applies since the SP_ERR_STAT does not indicate the DSP is in an error state.
An finally, my question is: can anyone recommend a SRIO DSP register I can poke to reset the SRIO port to set it in a state similar to a power on reset?
Cheers