OMAP-L138: EMAC interrupts control

UNA

Part Number: OMAP-L138

Hi,

I have qestion about EMAC interrupt contorl of OMAP-L138 after that the interrupt is mapped to a CPU interrupt, ARM9 core controls the EMAC module.

Q1: What is the interrupt core enable mask registers？, Please tell me specifically.

Q2: Why is it necessary by manipulating the interrupt core enable mask registers？

Best regads,
H.U

over 8 years ago

0 Cvetolin Shulev-XID over 8 years ago

TI__Guru 65405 points

I've forwarded this to the experts. Their feedback should be posted here.

BR
Tsvetolin Shulev

0 Yordan Kovachev over 8 years ago

TI__Guru**** 161600 points

Hi,

Have a look at Section 12.3.2 Interrupt Enabling through Section 12.3.6 Interrupt Prioritization of the device TRM.
The mentioned interrupt core enable mask registers (chip level) are:
System Interrupt Enable Set Register 1 through System Interrupt Enable Set Register 4 (ESR1 - ESR4).
And they are described in Section 12.4 AINTC Registers.

Hope this helps.

Best Regards,
Yordan

0 UNA over 8 years ago in reply to Yordan Kovachev

Mastermind 7980 points

Hi Yordan,

Thank you for your reply.
I understood the chip level registers. I am waiting for answers about Q2.

Best regards,
H.U

0 Mukul Bhatnagar over 8 years ago in reply to UNA

TI__Guru* 84565 points

On Q2

I think the intent of that sentence was that in general peripheral interrupts can arrive at any time (unpredictable) , so masking may be necessary and it is usually better to do this at the interrupt controller level rather than disabling the peripheral/module interrupts - this was interrupts can still qualify and pend when masked at the controller level.

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OMAP-L138: EMAC interrupts control