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TMS320C6472: CSL Cache Disable

npb17
Expert 1615 points

Part Number: TMS320C6472

I would like to disable cache for a region of external DDR, 0xEA000000 to 0xEB000000. 


Can someone confirm that CACHE_EMIFA_CE10 is the correct constant to use for that region?

This document is confusing about which is correct for the C6472.

www.ti.com/.../spru401j.pdf

  • 0
    TI__Guru**** 161600 points
    Hi,

    I've notified the design team. Their feedback will be posted here.

    Best Regards,
    Yordan
  • 0
    TI__Guru* 84110 points
    Nick,

    It is odd that we sometimes use CACHE_EMIFA_CE10 and sometimes CACHE_EMIFA_CE010 for that constant. I assume that is what you are asking about since the comments in the API ref guide clearly state the address range.

    The answer will depend on the version of CSL and other build-time constants that you are using. I would try them both and see which one works. Or you can do a search for the definition of the symbol from within CCS and see if it is enabled or greyed out.

    If this is not the answer you were looking for, please give us some more information such as which API you want to use, which OS you are using (TI-RTOS?) and so on.

    Regards,
    RandyP
  • 0
    TI__Mastermind 30365 points
    Nick,

    To add to Randy's reply, I would suggest taking a look at section 2.3 of www.ti.com/.../spru862b.pdf and page 105 of www.ti.com/.../spru871k.pdf (MAR 234 is for region EA00 0000h - EAFF FFFFh)

    Also if you see \csl_c6472_03_00_07_01\csl_c6472\inc\csl_cache.h of the CSL from here software-dl.ti.com/.../index_FDS.html line 117 defines CACHE_EMIFA_CE10 = 234 inside the CE_MAR struct.

    www.ti.com/.../spru401j.pdf is a generic C6000 API ref guide which may not be clear specifically for C6472.

    I understand my response might be piecemeal, but hopefully this will clarify.

    Lali
  • 0 in reply to RandyP
    Expert 1615 points

    I will check versions today.

    I was referring to that 010 vs 10 convention, but also the doc didn't say C64x specifically.  Presuming it was the last set of values.

    The actual issue I saw was: I attempted to reserve that address range for peripheral access (created a section in the Platform.xdc) and hence wanted to turn off caching.   When I built my image, there was some issue booting all the cores.  However, I have since realized it was probably a shortage of stack/heap and not the disabling of caching.

  • 0 in reply to npb17
    Expert 1615 points

    We are using CSL 03.00.07.01, with BIOS 6.34.04.22, if that matters.