PCIE Phy Loopback mode on C6657 no access in data area

*********************************************************
Code Common.h
*********************************************************
.......

// Test Configuration 
//#define GEN2               // <----- disabled for a complete init phase without errors
#define PCIE_REV0_HW
#define PCIESS1_X2           // <----- needed to activate two lanes
#define ENABLE_PHYLOOPBACK   // <----- needed to have phy Loopback configuration addons


#define CR "\n"
#define DIR_CHAR "//"
#define PCIE_logPrintf(...)                                                           \
{  char bufData[100];                                                                 \
   deltaTime(bufData);                                                                \
   platform_write("\n%s %s@%d:\t", bufData, 1+strrchr(__FILE__, DIR_CHAR), __LINE__); \
   platform_write(__VA_ARGS__);                                                       \
}


/* Outbound Base Address for PCIe Master */
#define PCIE_OB_LO_ADDR_M 0x70000000
#define PCIE_OB_HI_ADDR_M 0

/* Inbound Base Address for PCIe Master */
#define PCIE_IB_LO_ADDR_M 0x90000000
#define PCIE_IB_HI_ADDR_M 0

/* BAR Index PCie*/
#define PCIE_BAR_IDX_M 1

/* PCIe Regions used in the example */
#define PCIE_IB_REGION_M 0
#define PCIE_OB_REGION_M 0



/* last element in the buffer is a marker that indicates the buffer status: full/empty */
#define PCIE_EXAMPLE_MAX_CACHE_LINE_SIZE 128
#define PCIE_EXAMPLE_UINT32_SIZE           4 /* preprocessor #if requires a real constant, not a sizeof() */

#define PCIE_EXAMPLE_DSTBUF_BYTES ((PCIE_BUFSIZE_APP + 1) * PCIE_EXAMPLE_UINT32_SIZE)
#define PCIE_EXAMPLE_DSTBUF_REM (PCIE_EXAMPLE_DSTBUF_BYTES % PCIE_EXAMPLE_MAX_CACHE_LINE_SIZE)
#define PCIE_EXAMPLE_DSTBUF_PAD (PCIE_EXAMPLE_DSTBUF_REM ? (PCIE_EXAMPLE_MAX_CACHE_LINE_SIZE - PCIE_EXAMPLE_DSTBUF_REM) : 0)

typedef struct dstBuf_s
{
   volatile uint32_t buf[PCIE_BUFSIZE_APP + 1];
   /* Cache coherence: Must pad to cache line size in order to enable cacheability */
#if PCIE_EXAMPLE_DSTBUF_PAD
   uint8_t padding[PCIE_EXAMPLE_DSTBUF_PAD];
#endif
} dstBuf_t;


.....



*********************************************************
Code .c
*********************************************************
#include "Common.h"
#include <ti/drv/pcie/soc/pcie_soc.h>

Pcie_Handle handle = NULL;

Int PciExMessageTransmit(Pcie_Handle handle, volatile uint32_t *srcBuf);
Int PciExMessageReceive(void);



#pragma DATA_SECTION(dstBuf, ".dstBufSec")
/* Cache coherence: Align must be a multiple of cache line size (L2=128 bytes, L1=64 bytes) to operate with cache enabled. */
/* Aligning to 256 bytes because the PCIe inbound offset register masks the last 8bits of the buffer address  */
#pragma DATA_ALIGN(dstBuf, 256)




dstBuf_t dstBuf;

#define PCIE_EXAMPLE_BUF_EMPTY 0
#define PCIE_EXAMPLE_BUF_FULL  1

/* Does not need to be aligned (even for cache) since it is only accessed locally */
uint32_t srcBuf[PCIE_BUFSIZE_APP];

extern volatile unsigned int cregister TSCL;

/* Global config variable that controls
   the PCIe mode. It is global so it can be poked
   from CCS. It should be set either to EP or RC. */
pcieMode_e PcieModeGbl = pcie_RC_MODE;


void cache_invalidate(void *ptr, int size)
{
  uint32_t key;

  /* Disable Interrupts */
  key = _disable_interrupts();

  /*  Cleanup the prefetch buffer also. */
CSL_BootCfgUnlockKicker();
  CSL_XMC_invalidatePrefetchBuffer();
CSL_BootCfgLockKicker();

  CACHE_invL1d(ptr, size, CACHE_FENCE_WAIT);
  CACHE_invL2(ptr, size, CACHE_FENCE_WAIT);

  /* Reenable Interrupts. */
  _restore_interrupts(key);
}


void cache_writeback(void *ptr, int size)
{
  uint32_t key;
  /* Disable Interrupts */
  key = _disable_interrupts();

  CACHE_wbL1d(ptr, size, CACHE_FENCE_WAIT);
  CACHE_wbL2(ptr, size, CACHE_FENCE_WAIT);

  /* Reenable Interrupts. */
  _restore_interrupts(key);
}

/*****************************************************************************
 * Function: Power domain configuration
 ****************************************************************************/
pcieRet_e pciePowerCfg(void)
{
  CSL_BootCfgUnlockKicker();

  /* Turn on the PCIe power domain */
  if (CSL_PSC_getPowerDomainState(CSL_PSC_PD_PCIEX) != PSC_PDSTATE_ON)
  {
    /* Enable the domain */
    CSL_PSC_enablePowerDomain(CSL_PSC_PD_PCIEX);
    /* Enable MDCTL */
    CSL_PSC_setModuleNextState(CSL_PSC_LPSC_PCIEX, PSC_MODSTATE_ENABLE);
    /* Apply the domain */
    CSL_PSC_startStateTransition(CSL_PSC_PD_PCIEX);
    /* Wait for it to finish */
    while (!CSL_PSC_isStateTransitionDone(CSL_PSC_PD_PCIEX))
       ;
    CSL_BootCfgLockKicker();
  }
  else
  {
    CSL_BootCfgLockKicker();
    PCIE_logPrintf("Power domain is already enabled.  You probably re-ran without device reset (which is OK)"CR);
  }

  return pcie_RET_OK;
}


/*****************************************************************************
 * Function: Utility function to introduce delay 
 ****************************************************************************/
void cycleDelay(uint32_t count)
{
  uint32_t sat;

  if (count <= 0)
    return;

  sat = TSCL + count;
  while (TSCL < sat)
     ;
}


/*****************************************************************************
 * Function: Serdes configuration 
 ****************************************************************************/
pcieRet_e pcieSerdesCfg(void)
{
  uint16_t cfg;
  
  CSL_BootCfgUnlockKicker();

  /* Provide PLL reference clock to SERDES inside PCIESS
     Program PLL settings and enable PLL from PCIe SERDES.*/
  cfg = 0x01C9; /* value based on PCIe userguide */
  CSL_BootCfgSetPCIEConfigPLL(cfg);
  
  CSL_BootCfgLockKicker();

  /*Wait for PLL to lock (3000 CLKIN1 cycles) */
  cycleDelay(10000);
  
  return pcie_RET_OK;
}


/*****************************************************************************
 * Function: Enable/Disable LTSSM (Link Training)
 ****************************************************************************/
pcieRet_e pcieLtssmCtrl(Pcie_Handle handle, uint8_t enable)
{
  pcieRet_e                retVal;
  pcieCmdStatusReg_t       cmdStatus;
  pcieTiConfDeviceCmdReg_t deviceCmd;
  pcieRegisters_t          regs;

  memset(&deviceCmd, 0, sizeof(deviceCmd));
  memset(&cmdStatus, 0, sizeof(cmdStatus));
  memset(&regs,      0, sizeof(regs));

  regs.cmdStatus = &cmdStatus;
  if ((retVal = Pcie_readRegs(handle, pcie_LOCATION_LOCAL, &regs)) != pcie_RET_OK)
  {
     if (retVal == pcie_RET_INV_REG)
     {
        /* The cmdStatus register doesn't exist; try the deviceCmd instead */
        regs.cmdStatus       = NULL;
        regs.tiConfDeviceCmd = &deviceCmd;
        if ((retVal = Pcie_readRegs(handle, pcie_LOCATION_LOCAL, &regs)) != pcie_RET_OK)
        {
           PCIE_logPrintf("Read CMD STATUS and DEVICE CMD registers failed!."CR);

           return retVal;
        }
     }
     else
     {
        PCIE_logPrintf("Read CMD STATUS register failed!."CR);

        return retVal;
     }
  }
  
  if (enable)
     deviceCmd.ltssmEn = cmdStatus.ltssmEn = 1;
  else  
     deviceCmd.ltssmEn = cmdStatus.ltssmEn = 0;

  if ((retVal = Pcie_writeRegs(handle, pcie_LOCATION_LOCAL, &regs)) != pcie_RET_OK)
  {
    PCIE_logPrintf("SET CMD STATUS register failed!"CR);

    return retVal;
  }

  return pcie_RET_OK;
}


/*****************************************************************************
 * Function: Configure PCIe in Gen1 vs Gen2 mode
 ****************************************************************************/
static pcieRet_e pcieSetGen2(Pcie_Handle handle)
{
   pcieRet_e              retVal;
   pcieRegisters_t        regs;
   pcieLinkCapReg_t       linkCap;
   pcieGen2Reg_t          gen2;
   uint8_t                targetGen, dirSpd;

#ifdef GEN2
    targetGen = 2; // 5Gb/s
    dirSpd    = 1;
#else
    targetGen = 1; // 2.5Gb/s
    dirSpd    = 0;
#endif

    /* Setting PL_GEN2 */
    memset(&gen2,    0, sizeof(gen2));
    memset(&linkCap, 0, sizeof(linkCap));
    memset(&regs,    0, sizeof(regs));

   /* Set gen1/gen2 in link cap */
   regs.linkCap = &linkCap;
   if ((retVal = Pcie_readRegs(handle, pcie_LOCATION_LOCAL, &regs)) != pcie_RET_OK)
   {
      PCIE_logPrintf("GET linkCap register failed!."CR);

      return retVal;
   }

   if (linkCap.maxLinkSpeed != targetGen)
   {
      PCIE_logPrintf("PowerUP linkCap gen=%d change to %d"CR, linkCap.maxLinkSpeed, targetGen);
      linkCap.maxLinkSpeed = targetGen;
   }
   else
   {
      regs.linkCap = NULL; /* Nothing to write back */
   }

   gen2.numFts = 0xF;
   gen2.dirSpd = dirSpd;
#ifdef PCIESS1_X2
   gen2.lnEn   = 2;
#else
   gen2.lnEn   = 1;
#endif

   regs.gen2 = &gen2;
   if ((retVal = Pcie_writeRegs(handle, pcie_LOCATION_LOCAL, &regs)) != pcie_RET_OK)
   {
     PCIE_logPrintf("SET GEN2 register failed!"CR);

     return retVal;
   }

   PCIE_logPrintf("SET GEN2/link cap register OK!."CR);

   return retVal;
}


/*****************************************************************************
 * Function: Enable/Disable DBI writes
 ****************************************************************************/
static pcieRet_e pcieCfgDbi(Pcie_Handle handle, uint8_t enable)
{
   pcieRegisters_t        regs;
   pcieRet_e              retVal;
   pcieCmdStatusReg_t     cmdStatus;

   /* Configure BAR Masks */
   /* First need to enable writing on BAR mask registers */
   memset(&regs,      0, sizeof(regs));
   memset(&cmdStatus, 0, sizeof(cmdStatus));

   regs.cmdStatus = &cmdStatus;
   if ((retVal = Pcie_readRegs(handle, pcie_LOCATION_LOCAL, &regs)) != pcie_RET_OK)
   {
     PCIE_logPrintf("Read CMD STATUS register failed!"CR);

     return retVal;
   }

   cmdStatus.dbi = enable;

   if ((retVal = Pcie_writeRegs(handle, pcie_LOCATION_LOCAL, &regs)) != pcie_RET_OK)
   {
     PCIE_logPrintf("SET CMD STATUS register failed!"CR);

     return retVal;
   }

   return retVal;
}


/*****************************************************************************
 * Function: Configure PCIe in Root Complex Mode
 ****************************************************************************/
pcieRet_e pcieCfgRC(Pcie_Handle handle)
{
  pcieRet_e              retVal;
  pcieObSizeReg_t        obSize;
  pcieType1Bar32bitIdx_t type1Bar32bitIdx;
  pcieStatusCmdReg_t     statusCmd;
  pcieDevStatCtrlReg_t   devStatCtrl;
  pcieAccrReg_t          accr;
  pcieRegisters_t        setRegs;
  pcieRegisters_t        getRegs;

  memset(&obSize,           0, sizeof(obSize));
  memset(&type1Bar32bitIdx, 0, sizeof(type1Bar32bitIdx));
  memset(&statusCmd,        0, sizeof(statusCmd));
  memset(&devStatCtrl,      0, sizeof(devStatCtrl));
  memset(&accr,             0, sizeof(accr));

  /*Disable link training*/ //step 6
  if ((retVal = pcieLtssmCtrl(handle, FALSE)) != pcie_RET_OK) 
  {
    PCIE_logPrintf("Failed to disable Link Training!"CR);

    return retVal;
  }

  /* Configure the size of the translation regions */   
  memset(&setRegs, 0, sizeof(setRegs));

  obSize.size    = pcie_OB_SIZE_8MB;

  setRegs.obSize = &obSize;
  if ((retVal = Pcie_writeRegs(handle, pcie_LOCATION_LOCAL, &setRegs)) != pcie_RET_OK)
  {
    PCIE_logPrintf("SET OB_SIZE register failed!"CR);

    return retVal;
  }

  /* Set gen2/link cap */
  if ((retVal = pcieSetGen2(handle)) != pcie_RET_OK)
  {
     PCIE_logPrintf("pcieSetGen2 failed!."CR);

     return retVal;
  }

  /* Configure BAR Masks */
  /* First need to enable writing on BAR mask registers */
  if ((retVal = pcieCfgDbi(handle, 1)) != pcie_RET_OK)
  {
     return retVal;
  }

  /* Configure Masks*/
  memset(&setRegs, 0, sizeof(setRegs));

  type1Bar32bitIdx.reg.reg32 = PCIE_BAR_MASK;
  type1Bar32bitIdx.idx       = 0; /* configure BAR 0*/

  setRegs.type1Bar32bitIdx = &type1Bar32bitIdx;
  if ((retVal = Pcie_writeRegs(handle, pcie_LOCATION_LOCAL, &setRegs)) != pcie_RET_OK)
  {
    PCIE_logPrintf("SET BAR MASK register failed!"CR);

    return retVal;
  }
  type1Bar32bitIdx.reg.reg32  = PCIE_BAR_MASK;
  type1Bar32bitIdx.idx        = 1; /* configure BAR 1*/

  if ((retVal = Pcie_writeRegs(handle, pcie_LOCATION_LOCAL, &setRegs)) != pcie_RET_OK)
  {
    PCIE_logPrintf("SET BAR MASK register failed!"CR);

    return retVal;
  }

  /* Disable writing on BAR Masks */
  if ((retVal = pcieCfgDbi(handle, 0)) != pcie_RET_OK)
  {
     return retVal;
  }

  /* Enable memory access and mastership of the bus */
  memset(&setRegs, 0, sizeof(setRegs));
  memset(&getRegs, 0, sizeof(getRegs));

  getRegs.statusCmd = &statusCmd;
  if ((retVal = Pcie_readRegs(handle, pcie_LOCATION_LOCAL, &getRegs)) != pcie_RET_OK)
  {
    PCIE_logPrintf("Read Status Comand register failed!"CR);

    return retVal;
  }

  statusCmd.memSp  = 1;
  statusCmd.busMs  = 1;
  statusCmd.resp   = 1;
  statusCmd.serrEn = 1;

  setRegs.statusCmd = &statusCmd;
  if ((retVal = Pcie_writeRegs(handle, pcie_LOCATION_LOCAL, &setRegs)) != pcie_RET_OK)
  {
    PCIE_logPrintf("SET Status Command register failed!"CR);

    return retVal;
  }

  /* Enable Error Reporting */
  memset(&setRegs, 0, sizeof(setRegs));
  memset(&getRegs, 0, sizeof(getRegs));

  getRegs.devStatCtrl = &devStatCtrl;
  if ((retVal = Pcie_readRegs(handle, pcie_LOCATION_LOCAL, &getRegs)) != pcie_RET_OK)
  {
    PCIE_logPrintf("Regad Device Status Control register failed!"CR);

    return retVal;
  }
 
  devStatCtrl.reqRp      = 1;
  devStatCtrl.fatalErRp  = 1;
  devStatCtrl.nFatalErRp = 1;
  devStatCtrl.corErRp    = 1;

  setRegs.devStatCtrl = &devStatCtrl;
  if ((retVal = Pcie_writeRegs(handle, pcie_LOCATION_LOCAL, &setRegs)) != pcie_RET_OK)
  {
    PCIE_logPrintf("SET Device Status Control register failed!"CR);

    return retVal;
  }

  /* Enable ECRC */
  memset(&setRegs, 0, sizeof(setRegs));
  
  accr.chkEn  = 1;
  accr.chkCap = 1;
  accr.genEn  = 1;
  accr.genCap = 1;

  setRegs.accr = &accr;
  if ((retVal = Pcie_writeRegs(handle, pcie_LOCATION_LOCAL, &setRegs)) != pcie_RET_OK)
  {
    PCIE_logPrintf("SET ACCR register failed!"CR);

    return retVal;
  }

  return pcie_RET_OK;
}


/*****************************************************************************
 * Function: Configure and enable Outbound Address Translation 
 ****************************************************************************/
pcieRet_e pcieObTransCfg(Pcie_Handle handle, uint32_t obAddrLo, uint32_t obAddrHi, uint8_t region)
{
  pcieRet_e            retVal;
  pcieRegisters_t      setRegs;
  pcieRegisters_t      getRegs;
  pcieCmdStatusReg_t   cmdStatus;

  memset(&setRegs,   0, sizeof(setRegs));
  memset(&getRegs,   0, sizeof(getRegs));
  memset(&cmdStatus, 0, sizeof(cmdStatus));

  /* Set outbound offset registers */
  if ((retVal = Pcie_cfgObOffset(handle, obAddrLo, obAddrHi, region)) != pcie_RET_OK) 
  {
    PCIE_logPrintf("Failed to configure ObOffset registers!"CR);

    return retVal;
  }

  /*enable Outbound address translation*/
  memset(&setRegs, 0, sizeof(setRegs));
  memset(&getRegs, 0, sizeof(getRegs));

  getRegs.cmdStatus = &cmdStatus;
  if ((retVal = Pcie_readRegs(handle, pcie_LOCATION_LOCAL, &getRegs)) != pcie_RET_OK)
  {
    PCIE_logPrintf("Read CMD STATUS register failed!"CR);

    return retVal;
  }

  cmdStatus.obXltEn = 1;

  setRegs.cmdStatus = &cmdStatus;
  if ((retVal = Pcie_writeRegs(handle, pcie_LOCATION_LOCAL, &setRegs)) != pcie_RET_OK)
  {
    PCIE_logPrintf("SET CMD STATUS register failed!"CR);

    return retVal;
  }

  return pcie_RET_OK;
}


/*****************************************************************************
 * Function: Configure and enable Inbound Address Translation 
 ****************************************************************************/
pcieRet_e pcieIbTransCfg(Pcie_Handle handle, pcieIbTransCfg_t *ibCfg)
{
  pcieRet_e            retVal;
  pcieRegisters_t      setRegs;
  pcieRegisters_t      getRegs;
  pcieCmdStatusReg_t   cmdStatus;

  memset(&setRegs,   0, sizeof(setRegs));
  memset(&getRegs,   0, sizeof(getRegs));
  memset(&cmdStatus, 0, sizeof(cmdStatus));

  /* Set outbound offset registers */
  if ((retVal = Pcie_cfgIbTrans(handle, ibCfg)) != pcie_RET_OK) 
  {
    PCIE_logPrintf("Failed to configure Inbound Translation registers!"CR);
    return retVal;
  }

  /*enable Inbound address translation*/
  memset(&setRegs, 0, sizeof(setRegs));
  memset(&getRegs, 0, sizeof(getRegs));

  getRegs.cmdStatus = &cmdStatus;
  if ((retVal = Pcie_readRegs(handle, pcie_LOCATION_LOCAL, &getRegs)) != pcie_RET_OK)
  {
    PCIE_logPrintf("Read CMD STATUS register failed!"CR);

    return retVal;
  }

  cmdStatus.ibXltEn = 1;

  setRegs.cmdStatus = &cmdStatus;
  if ((retVal = Pcie_writeRegs(handle, pcie_LOCATION_LOCAL, &setRegs)) != pcie_RET_OK)
  {
    PCIE_logPrintf("SET CMD STATUS register failed!"CR);

    return retVal;
  }

  return pcie_RET_OK;
}


/*****************************************************************************
 * Function: Configure PHY Loopback
 ****************************************************************************/
pcieRet_e pcieSerDesLoopback(Pcie_Handle handle)
{
  pcieRet_e            retVal;
  pcieRegisters_t      regs;
  pcieSerdesCfg0Reg_t  serdesCfg0;
  pcieSerdesCfg1Reg_t  serdesCfg1;

  memset(&regs,       0, sizeof(regs));
  memset(&serdesCfg0, 0, sizeof(serdesCfg0));
  memset(&serdesCfg1, 0, sizeof(serdesCfg1));

  regs.serdesCfg0 = &serdesCfg0;
  regs.serdesCfg1 = &serdesCfg1;
  if ((retVal = Pcie_readRegs(handle, pcie_LOCATION_LOCAL, &regs)) != pcie_RET_OK)
  {
     PCIE_logPrintf("Read SerdesCfg register failed!"CR);

     return retVal;
  }

  serdesCfg0.txLoopback = 0x2;
  serdesCfg0.rxLoopback = 0x3;
  serdesCfg0.rxLos      = 0;
  serdesCfg1.txLoopback = 0x2;
  serdesCfg1.rxLoopback = 0x3;
  serdesCfg1.rxLos      = 0;

  if ((retVal = Pcie_writeRegs(handle, pcie_LOCATION_LOCAL, &regs)) != pcie_RET_OK)
  {
     PCIE_logPrintf("SET SerdesCfg PHYLOOPBACK failed!"CR);

     return retVal;
  }

  return pcie_RET_OK;
}


/*****************************************************************************
 * Function: Configure POLL ACTIVE STATE
 ****************************************************************************/
pcieRet_e pcieForceLink(Pcie_Handle handle)
{
  pcieRet_e            retVal;
  pcieRegisters_t      regs;
  pciePlForceLinkReg_t plForceLink;

  memset(&regs,        0, sizeof(regs));
  memset(&plForceLink, 0, sizeof(plForceLink));

  regs.plForceLink = &plForceLink;
  if ((retVal = Pcie_readRegs(handle, pcie_LOCATION_LOCAL, &regs)) != pcie_RET_OK)
  {
     PCIE_logPrintf("Read plForceLink register failed!"CR);

     return retVal;
  }

  plForceLink.lnkState  = 0x2;
  plForceLink.forceLink = 0x1;

  if ((retVal = Pcie_writeRegs(handle, pcie_LOCATION_LOCAL, &regs)) != pcie_RET_OK)
  {
     PCIE_logPrintf("SET plForceLink failed!"CR);

     return retVal;
  }

  return pcie_RET_OK;
}


/*****************************************************************************
 * Function: Initialize application buffers
 ****************************************************************************/
void pcieInitAppBuf(void)
{
  uint32_t i;
  
  for (i = 0; i < PCIE_BUFSIZE_APP; i++)
  {
    dstBuf.buf[i] = 0;	
    srcBuf[i] = i;	
  }

  dstBuf.buf[PCIE_BUFSIZE_APP] = PCIE_EXAMPLE_BUF_EMPTY;
}


/*****************************************************************************
 * Function: Check LTSSM status and wait for the link to be up
 ****************************************************************************/
static int pcieWaitLinkUp(Pcie_Handle handle)
{
  pcieRegisters_t  getRegs;
  uint8_t          ltssmState = 0;
#ifdef PCIE_REV0_HW
  pcieDebug0Reg_t            ltssmStateReg;
#else
  pcieTiConfDeviceCmdReg_t   ltssmStateReg;
#endif

  do
  {
    memset(&getRegs, 0, sizeof(getRegs));
#ifdef PCIE_REV0_HW
    getRegs.debug0 =          &ltssmStateReg;
#else
     getRegs.tiConfDeviceCmd = &ltssmStateReg;
#endif
    memset(&ltssmStateReg,  0, sizeof(ltssmStateReg));
    cycleDelay(100);
    if (Pcie_readRegs(handle, pcie_LOCATION_LOCAL, &getRegs) != pcie_RET_OK)
    {
      PCIE_logPrintf("Read LTSSM state failed!\n");

      return -1;
    }
    ltssmState = ltssmStateReg.ltssmState;
    Task_sleep(10);
  }  while(ltssmState != pcie_LTSSM_L0);

  return 0;
}



/*****************************************************************************
 * Function: Converts a core local L2 address to a global L2 address 
 *   Input addr:  L2 address to be converted to global.
 *   return:  uint32_t   Global L2 address
 *****************************************************************************/
uint32_t pcieConvert_CoreLocal2GlobalAddr(uint32_t  addr)
{
  uint32_t coreNum;

  CSL_BootCfgUnlockKicker();

  /* Get the core number. */
  coreNum = CSL_chipReadReg(CSL_CHIP_DNUM); 
  CSL_BootCfgLockKicker();
  
  /* Compute the global address. */
  return ((1 << 28) | (coreNum << 24) | (addr & 0x00ffffff));
}    

static int pcieApplicationConfig(Pcie_Handle *handle)
{
   pcieIbTransCfg_t ibCfg;
   pcieBarCfg_t     barCfg;
   pcieRet_e        retVal;
   uint16_t         lock = 0;
   int              ret  = 0;

   /* Initialize application buffers */
   pcieInitAppBuf();

   /* Power up PCIe Module */
   if ((retVal = pciePowerCfg()) != pcie_RET_OK)
   {
     PCIE_logPrintf("PCIe Power Up failed (%d)"CR, (int)retVal);
     ret = 2;
     goto out;
   }

   if ((retVal = Pcie_open(0, handle)) != pcie_RET_OK)
   {
     PCIE_logPrintf("Open failed (%d)"CR, (int)retVal);
     ret = 3;
     goto out;
   }

   /* Set the PCIe mode*/
   retVal = Pcie_setInterfaceMode(*handle, PcieModeGbl);
   if (retVal != pcie_RET_OK)
   {
     PCIE_logPrintf("Set PCIe Mode failed (%d)"CR, (int)retVal);
     ret = 4;
     goto out;
   }

/* // Select onBoard PciEx clock generator
   PCIE_logPrintf("MuxSel value: 0x%X"CR, fpgaGetMuxSel());//read FPGA Reg 0x50
   fpgaSetMuxSel(0); // eval onboard PciEx CLK Generator
   PCIE_logPrintf("MuxSel value: 0x%X"CR, fpgaGetMuxSel());//read FPGA Reg 0x50
*/
   /* Configure SERDES*/
   if ((retVal = pcieSerdesCfg()) != pcie_RET_OK)
   {
     PCIE_logPrintf("PCIe Serdes config failed (%d)"CR, (int)retVal);
     ret = 5;
     goto out;
   }

   PCIE_logPrintf("PCIe Power Up."CR);

   /* Wait until the PCIe SERDES PLL locks */
   CSL_BootCfgUnlockKicker();
   while (!lock)
   {
     CSL_BootCfgGetPCIEPLLLock(&lock);
   }
   CSL_BootCfgLockKicker();

   PCIE_logPrintf("PLL configured."CR);


   /* Configure application registers for Root Complex*/
   if ((retVal = pcieCfgRC(*handle)) != pcie_RET_OK)
   {
     PCIE_logPrintf("Failed to configure PCIe in RC mode (%d)"CR, (int)retVal);
     ret = 6;
     goto out;
   }

   /* Configure Address Translation */
   barCfg.location = pcie_LOCATION_LOCAL;
   barCfg.mode     = pcie_RC_MODE;
   barCfg.base     = PCIE_IB_LO_ADDR_M;
   barCfg.prefetch = pcie_BAR_NON_PREF;
   barCfg.type     = pcie_BAR_TYPE32;
   barCfg.memSpace = pcie_BAR_MEM_MEM;
   barCfg.idx      = PCIE_BAR_IDX_M;

   if ((retVal = Pcie_cfgBar(*handle, &barCfg)) != pcie_RET_OK)
   {
     PCIE_logPrintf("Failed to configure BAR (%d)"CR, (int)retVal);
     ret = 7;
     goto out;
   }

   ibCfg.ibBar         = PCIE_BAR_IDX_M; /* Match BAR that was configured above*/
   ibCfg.ibStartAddrLo = PCIE_IB_LO_ADDR_M;
   ibCfg.ibStartAddrHi = PCIE_IB_HI_ADDR_M;
   ibCfg.ibOffsetAddr  = (uint32_t)pcieConvert_CoreLocal2GlobalAddr ((uint32_t)dstBuf.buf);
   ibCfg.region        = PCIE_IB_REGION_M;

   if ((retVal = pcieIbTransCfg(*handle, &ibCfg)) != pcie_RET_OK)
   {
     PCIE_logPrintf("Failed to configure Inbound Translation (%d)"CR, (int)retVal);
     ret = 8;
     goto out;
   }
   else
   {
     PCIE_logPrintf("Successfully configured Inbound Translation!"CR);
   }

   retVal = pcieObTransCfg(*handle, PCIE_OB_LO_ADDR_M, PCIE_OB_HI_ADDR_M, PCIE_OB_REGION_M);
   if (retVal != pcie_RET_OK)
   {
     PCIE_logPrintf("Failed to configure Outbound Address Translation (%d)"CR, (int)retVal);
     ret = 9;
     goto out;
   }
   else
   {
     PCIE_logPrintf("Successfully configured Outbound Translation!"CR);
   }

out:

   return ret;
}


pcieRet_e pcieCheckLinkParams(Pcie_Handle handle)
{
  pcieRet_e retVal = pcie_RET_OK;
  pcieRegisters_t regs;
  pcieLinkStatCtrlReg_t linkStatCtrl;
  int32_t expLanes = 1, expSpeed = 1;
  const char *pass = "PASS", *fail = "FAIL";
  const char *result = pass;

#ifdef GEN2
  expSpeed = 2;
#endif
#ifdef PCIESS1_X2
  expLanes = 2;
#endif

  /* Get link status */
  PCIE_logPrintf("Checking link speed and # of lanes"CR);
  memset(&regs, 0, sizeof(regs));

  regs.linkStatCtrl = &linkStatCtrl;
  retVal = Pcie_readRegs(handle, pcie_LOCATION_LOCAL, &regs);
  if (retVal != pcie_RET_OK)
  {
     PCIE_logPrintf ("Failed to read linkStatCtrl: %d\n", retVal);
  }
  else
  {
    /* Check number of lanes */
    if (expLanes != linkStatCtrl.negotiatedLinkWd)
    {
       result = fail;
       retVal = pcie_RET_UNSUPPORTED;
    }
    else
    {
       result = pass;
    }
    PCIE_logPrintf("Expect %d lanes, found %d lanes (%s)"CR,
                   (int)expLanes, (int)linkStatCtrl.negotiatedLinkWd, result);

    /* Check speed */
    if (expSpeed != linkStatCtrl.linkSpeed)
    {
       result = fail;
       retVal = pcie_RET_UNSUPPORTED;
    }
    else
    {
       result = pass;
    }
    PCIE_logPrintf("Expect gen %d speed, found gen %d speed (%s)"CR,
                   (int)expSpeed, (int)linkStatCtrl.linkSpeed, result);
  }

  return retVal;
}


/*****************************************************************************
 * Function: Main 
 ****************************************************************************/
Void PciExMain(UArg arg0, UArg arg1)
{
  int       ret = 0;
  pcieRet_e retVal;
  uint32_t  i;

  TSCL = 1;

  CSL_BootCfgUnlockKicker();
  PcieModeGbl = (pcieMode_e)CSL_BootCfgGetPCIEMode();
  PCIE_logPrintf("PCIESS is %s", (CSL_BootCfgIsPCIEEnabled() == TRUE) ? "enabled" : "disabled");
  CSL_BootCfgLockKicker();

  PCIE_logPrintf("**********************************************"CR);
  PCIE_logPrintf("*             PCIe Test Start                *"CR);
  PCIE_logPrintf("*                RC mode                     *"CR);
  PCIE_logPrintf("**********************************************"CR);

  PCIE_logPrintf("Version #: 0x%08x; string %s"CR, Pcie_getVersion(), Pcie_getVersionStr());

  /* Pass device config to LLD*/
  if ((retVal = Pcie_init(&pcieInitCfg)) != pcie_RET_OK)
  {
    PCIE_logPrintf("LLD device configuration failed."CR);
    ret = 1;
    goto out;
  }

  ret = pcieApplicationConfig(&handle);
  if (ret != 0)
  {
    goto out;
  }

#ifdef ENABLE_PHYLOOPBACK
  PCIE_logPrintf("Configure PHY Loopback..."CR);
  pcieSerDesLoopback(handle);
#endif

  PCIE_logPrintf("Starting link training..."CR);

  /*Enable link training*/
  if ((retVal = pcieLtssmCtrl(handle, TRUE)) != pcie_RET_OK) 
  {
    PCIE_logPrintf("Failed to Enable Link Training!"CR, (int)retVal);
    ret = 14;
    goto out;
  }

#ifdef ENABLE_PHYLOOPBACK
   PCIE_logPrintf("Force PCIe Link state..."CR);
   pcieForceLink(handle);
#endif

  /* Wait for link to be up */
  while (pcieWaitLinkUp(handle) < 0)
  {
    PCIE_logPrintf("pcieWaitLinkUp fail."CR);
    //my_usleep(1000);
    cycleDelay(100);
  }
  PCIE_logPrintf("Link is up."CR);
  my_sleep(10); // wait ~ 10 sec

  if ((retVal = pcieCheckLinkParams(handle)) != pcie_RET_OK)
  {
    PCIE_logPrintf("Link width/speed verification FAILed: %d"CR, retVal);
  }

  do
  {
    // Write from RC
    while (PciExMessageTransmit(handle, srcBuf) < 0)
      Task_sleep(100);
    
    // Wait the message
    if (PciExMessageReceive() > 0)
    {
      /* check all the data */
      for (i = 0; i < PCIE_BUFSIZE_APP; i++)
      {
        if (dstBuf.buf[i] != srcBuf[i])
        {
          PCIE_logPrintf("Received data = %d\nTransmited data = %d\nIndex = %d.\n\nTest failed."CR,
                         dstBuf.buf[i], srcBuf[i], i);
          goto out;
        } 
        dstBuf.buf[PCIE_BUFSIZE_APP] = PCIE_EXAMPLE_BUF_EMPTY;
      }
    }
    my_sleep(10); // wait ~ 10 sec
  } while (1);

out:
  quitCmd(0, NULL);
  DBG_PRINTF("Exit %s", __func__);

  Task_exit();
}



Int PciExMessageReceive(void)
{
   pcieRet_e        retVal;

   do
   {
      cache_invalidate((void *)dstBuf.buf, PCIE_EXAMPLE_DSTBUF_BYTES);
      if (global_var->exit_flag == TRUE)
         break;

    } while (*(volatile uint32_t*)(dstBuf.buf[PCIE_BUFSIZE_APP]) != PCIE_EXAMPLE_BUF_FULL);

   return 0;
}


Int PciExMessageTransmit(Pcie_Handle handle, volatile uint32_t *srcBuf)
{
   uint32_t           i;
   pcieRet_e          retVal;
   void               *pcieBase;
   volatile uint32_t  *pciedstBufBase;

   /* Loopback to RC what was written in the DST buffer.
      Write from EP to RC */
   if ((retVal = Pcie_getMemSpaceRange(handle, &pcieBase, NULL)) != pcie_RET_OK)
   {
     PCIE_logPrintf("getMemSpaceRange failed"CR, (int)retVal);

     return -1;
   }
   pciedstBufBase = (volatile uint32_t *)pcieBase;

  while (pciedstBufBase[PCIE_BUFSIZE_APP] == PCIE_EXAMPLE_BUF_FULL)
    Task_sleep(1000);

  for (i = 0; i < PCIE_BUFSIZE_APP; i++)
  {
    pciedstBufBase[i] = srcBuf[i];
  }

  //Mark that the buffer is full, so RC can process it
  pciedstBufBase[PCIE_BUFSIZE_APP] = PCIE_EXAMPLE_BUF_FULL;

 return 0;
}













***************************************************************
Serial.log
***************************************************************


00:00:00 00:00:07 myPciExDemo_PhyLoop.c:.PCIESS is enabled
00:00:00 00:00:00 myPciExDemo_PhyLoop.c:.**********************************************
00:00:00 00:00:00 myPciExDemo_PhyLoop.c:.*             PCIe Test Start                *
00:00:00 00:00:00 myPciExDemo_PhyLoop.c:.*                RC mode                     *
00:00:00 00:00:00 myPciExDemo_PhyLoop.c:.**********************************************
00:00:00 00:00:00 myPciExDemo_PhyLoop.c:.Version #: 0x02020007; string PCIE LLD Revision: 02.02.00.07:Dec 13 2016:16:29:29
00:00:00 00:00:00 myPciExDemo_PhyLoop.c:.
00:00:00 00:00:00 myPciExDemo_PhyLoop.c:.MuxSel value: 0x0
00:00:00 00:00:00 myPciExDemo_PhyLoop.c:.MuxSel value: 0x0
00:00:00 00:00:00 myPciExDemo_PhyLoop.c:.PCIe Power Up.
00:00:00 00:00:00 myPciExDemo_PhyLoop.c:.PLL configured.
00:00:00 00:00:00 myPciExDemo_PhyLoop.c:.SET GEN2/link cap register OK!.
00:00:00 00:00:00 myPciExDemo_PhyLoop.c:.Successfully configured Inbound Translation!
00:00:00 00:00:00 myPciExDemo_PhyLoop.c:.Successfully configured Outbound Translation!
00:00:00 00:00:00 myPciExDemo_PhyLoop.c:.Configure PHY Loopback...
00:00:00 00:00:00 myPciExDemo_PhyLoop.c:.Starting link training...
00:00:00 00:00:00 myPciExDemo_PhyLoop.c.:.Force PCIe Link state...
00:00:00 00:00:00 myPciExDemo_PhyLoop.c:.Start PciExMsgCmd taskname "PciExMsg"
00:00:00 00:00:00 myPciExDemo_PhyLoop.c:.Link is up.
00:00:07 00:00:07 myPciExDemo_PhyLoop.c:.Checking link speed and # of lanes
00:00:07 00:00:00 myPciExDemo_PhyLoop.c:.Expect 2 lanes, found 2 lanes (PASS)
00:00:07 00:00:00 myPciExDemo_PhyLoop.c:.Expect gen 1 speed, found gen 1 speed (PASS)




***************************************************************
main.cfg
***************************************************************
var Memory              = xdc.useModule('xdc.runtime.Memory');
var BIOS                = xdc.useModule('ti.sysbios.BIOS');
var Task                = xdc.useModule('ti.sysbios.knl.Task');
var HeapBuf             = xdc.useModule('ti.sysbios.heaps.HeapBuf');
var Log                 = xdc.useModule('xdc.runtime.Log');
var Hwi                 = xdc.useModule('ti.sysbios.hal.Hwi');
var Swi                 = xdc.useModule('ti.sysbios.knl.Swi');
var Timer                 = xdc.useModule('ti.sysbios.hal.Timer');

var SwTimerPrms           = new Timer.Params();
SwTimerPrms.startMode     = Timer.StartMode_AUTO;
SwTimerPrms.period        = 100000;        // 100,000 uSecs = 100ms
SwTimerPrms.instance.name = "SWTimer";
var SwTimer               = Timer.create(null, '&swthTimerHandler', SwTimerPrms);

Task.common$.namedInstance     = true;

var Clock        =   xdc.useModule('ti.sysbios.knl.Clock');
Clock.tickPeriod = 750;

var Sem          = xdc.useModule('ti.sysbios.knl.Semaphore');
var Diags           = xdc.useModule('xdc.runtime.Diags');

var devType         = "c6657";
var Csl             = xdc.useModule('ti.csl.Settings');
Csl.deviceType      = devType;
Csl.useCSLIntcLib   = true;

var osType          = "tirtos"
var Osal            = xdc.useModule('ti.osal.Settings');
Osal.osType         = osType;
var Qmss               = xdc.loadPackage('ti.drv.qmss');
var Emac               = xdc.loadPackage('ti.drv.emac');
Emac.Settings.socType  = devType;
var Nimu               = xdc.loadPackage('ti.transport.ndk.nimu');
Nimu.Settings.socType  = devType;
var Defaults = xdc.useModule('xdc.runtime.Defaults');

var LoggerBuf       = xdc.useModule('xdc.runtime.LoggerBuf');
var Exc             = xdc.useModule('ti.sysbios.family.c64p.Exception');
Exc.common$.logger  = LoggerBuf.create();
Exc.enablePrint     = true;
var Global    = xdc.useModule('ti.ndk.config.Global');
Global.enableCodeGeneration = false;
var Cache       =   xdc.useModule('ti.sysbios.family.c66.Cache');
var Startup       = xdc.useModule('xdc.runtime.Startup');
var System        = xdc.useModule('xdc.runtime.System');
var Settings      = xdc.useModule('ti.sysbios.posix.Settings');
Settings.supportsMutexPriority = true;

var HeapMem               = xdc.useModule('ti.sysbios.heaps.HeapMem');
var heapMemParams         = new HeapMem.Params();
heapMemParams.size        = 0x36000; /// **********************

heapMemParams.sectionName = "systemHeap";
Program.global.heap0      = HeapMem.create(heapMemParams);


Memory.defaultHeapInstance     = Program.global.heap0;
Program.sectMap["sharedL2"]    = "MSMCSRAM"; 
Program.sectMap["systemHeap"]  = "MSMCSRAM";
Program.sectMap[".sysmem"]     = "MSMCSRAM";
Program.sectMap[".args"]       = "MSMCSRAM";
Program.sectMap[".cio"]        = "MSMCSRAM";
Program.sectMap[".rodata"]     = "MSMCSRAM";
Program.sectMap[".neardata"]   = "MSMCSRAM";
Program.sectMap[".init_array"] = "MSMCSRAM";
Program.sectMap[".cinit"]      = "MSMCSRAM";
Program.sectMap[".bss"]        = "MSMCSRAM";
Program.sectMap[".const"]      = "MSMCSRAM";
Program.sectMap[".text"]       = "MSMCSRAM";
Program.sectMap[".code"]       = "MSMCSRAM";
Program.sectMap[".switch"]     = "MSMCSRAM";
Program.sectMap[".data"]       = "MSMCSRAM";
Program.sectMap[".vecs"]       = "MSMCSRAM";
Program.sectMap["emacComm"]    = "L2SRAM";
Program.sectMap[".far:taskStackSection"] = "L2SRAM";
Program.sectMap[".stack"]      =  "L2SRAM";
Program.sectMap["platform_lib"]         = "L2SRAM";
Program.sectMap[".fardata:benchmarking"] = "DDR3";
Program.sectMap[".dstBufSec"] = "L2SRAM";
Program.sectMap[".testData"] = "L2SRAM";

SysStd              = xdc.useModule('xdc.runtime.SysStd');
System.SupportProxy = SysStd;
BIOS.taskEnabled         =   true;


var Edma     = xdc.loadPackage ("ti.sdo.edma3.drv.sample");
var drv      = xdc.loadPackage ("ti.sdo.edma3.drv");
var rm       = xdc.loadPackage ("ti.sdo.edma3.rm");
var Event    = xdc.useModule('ti.sysbios.knl.Event');
var Idle     = xdc.useModule('ti.sysbios.knl.Idle');
var CpIntc   = xdc.useModule('ti.sysbios.family.c66.tci66xx.CpIntc');
var ECM      = xdc.useModule ("ti.sysbios.family.c64p.EventCombiner");
var C64_Hwi  = xdc.useModule ("ti.sysbios.family.c64p.Hwi");
var halCache = xdc.useModule('ti.sysbios.hal.Cache');

ECM.eventGroupHwiNum[0] = 7;
ECM.eventGroupHwiNum[1] = 8;

Task.addHookSet({ registerFxn: '&TaskRegisterId', switchFxn: '&mySwitch', });

var Utils = xdc.loadPackage('ti.utils.profiling');
var Pcie    = xdc.loadPackage('ti.drv.pcie');
Pcie.Settings.enableProfiling = true;
Pcie.Settings.socType = devType; /* use soc/c6657/src/pcie_soc.c */

BIOS.smpEnabled = true;
Clock.timerId = -1;
Clock.swiPriority = 15;
Global.IPv6 = false;