AM5718: idkAM571x does not implement workaround for errata i872

Hi-

I am working with a custom board that uses a modified idkAM571x board library.  I spent the past few days debugging erratic DDR memory behavior.  Ultimately, this was caused by errata i872, which was not accounted for in the idkAM571x board library.  The following code is from idkAM571x_clock.c:

 CSL_FINST(dsp1CmReg->CM_DSP1_CLKSTCTRL_REG,
        DSP1_CM_CORE_AON_CM_DSP1_CLKSTCTRL_REG_CLKTRCTRL, SW_WKUP);
/*
    while(CSL_DSP1_CM_CORE_AON_CM_DSP1_CLKSTCTRL_REG_CLKACTIVITY_DSP1_GFCLK_ACT !=
       CSL_FEXT(dsp1CmReg->CM_DSP1_CLKSTCTRL_REG,
        DSP1_CM_CORE_AON_CM_DSP1_CLKSTCTRL_REG_CLKACTIVITY_DSP1_GFCLK));
*/

    CSL_FINST(dsp2CmReg->CM_DSP2_CLKSTCTRL_REG,
        DSP2_CM_CORE_AON_CM_DSP2_CLKSTCTRL_REG_CLKTRCTRL, SW_WKUP);
/*
    while(CSL_DSP2_CM_CORE_AON_CM_DSP2_CLKSTCTRL_REG_CLKACTIVITY_DSP2_GFCLK_ACT !=
       CSL_FEXT(dsp2CmReg->CM_DSP2_CLKSTCTRL_REG,
        DSP2_CM_CORE_AON_CM_DSP2_CLKSTCTRL_REG_CLKACTIVITY_DSP2_GFCLK));
*/

    CSL_FINST(ivaCmReg->CM_IVA_CLKSTCTRL_REG,
        IVA_CM_CORE_CM_IVA_CLKSTCTRL_REG_CLKTRCTRL, SW_WKUP);
/*
    while(CSL_IVA_CM_CORE_CM_IVA_CLKSTCTRL_REG_CLKACTIVITY_IVA_GCLK_ACT !=
       CSL_FEXT(ivaCmReg->CM_IVA_CLKSTCTRL_REG,
        IVA_CM_CORE_CM_IVA_CLKSTCTRL_REG_CLKACTIVITY_IVA_GCLK));
*/

    /* PRCM Generic module mode setting functions */

    CSL_FINST(camCmReg->CM_CAM_VIP1_CLKCTRL_REG,
        CAM_CM_CORE_CM_CAM_VIP1_CLKCTRL_REG_MODULEMODE, AUTO);

    while(CSL_CAM_CM_CORE_CM_CAM_VIP1_CLKCTRL_REG_IDLEST_FUNC !=
       CSL_FEXT(camCmReg->CM_CAM_VIP1_CLKCTRL_REG,
        CAM_CM_CORE_CM_CAM_VIP1_CLKCTRL_REG_IDLEST));

Now when modifying the board library for our custom board, I commented out the clock configuration for DSP2, IVA, and VIPs (these are not necessary in our application).  When doing so, however, I all of a sudden saw erratic DDR memory behavior (DDR memory was constantly changing in no discernible pattern).  After much investigation, I found that adding a ~1 microsecond delay after DSP1 CD wakeup and remaining clock configuration of the function resolved the erratic behavior.  I finally found errata i872 and implemented the workaround (so the modified configuration is as follows):

    // CTRL-29794: Due to errata i872, we ensure the DSP is powered-up and clocked for a brief time
    // before enabling the DDR-related clocks below. Follow the sequence provided in errata i872.
    // Start a SW force wakeup for DSPSS.
    CSL_FINST(dsp1CmReg->CM_DSP1_CLKSTCTRL_REG,
        DSP1_CM_CORE_AON_CM_DSP1_CLKSTCTRL_REG_CLKTRCTRL, SW_WKUP);

    // Enable DSPSS clock.
    CSL_FINST(dsp1CmReg->CM_DSP1_DSP1_CLKCTRL_REG,
        DSP1_CM_CORE_AON_CM_DSP1_DSP1_CLKCTRL_REG_MODULEMODE, AUTO);

    // Reset de-assertion for DSP SS logic.
    CSL_FINST(dsp1PrmReg->RM_DSP1_RSTCTRL_REG,
        DSP1_PRM_RM_DSP1_RSTCTRL_REG_RST_DSP1, CLEAR);

    // Wait until the module is functional.
    while(CSL_DSP1_CM_CORE_AON_CM_DSP1_DSP1_CLKCTRL_REG_IDLEST_FUNC != 
        CSL_FEXT(dsp1CmReg->CM_DSP1_DSP1_CLKCTRL_REG,
         DSP1_CM_CORE_AON_CM_DSP1_DSP1_CLKCTRL_REG_IDLEST));

/*
    while(CSL_DSP1_CM_CORE_AON_CM_DSP1_CLKSTCTRL_REG_CLKACTIVITY_DSP1_GFCLK_ACT !=
       CSL_FEXT(dsp1CmReg->CM_DSP1_CLKSTCTRL_REG,
        DSP1_CM_CORE_AON_CM_DSP1_CLKSTCTRL_REG_CLKACTIVITY_DSP1_GFCLK));
*/

With the workaround implemented, I can now disable clock configuration of DSP2/IVA/VIPs without affecting DDR performance.  I suspect that those extra clock configurations on the idkAM571x were providing sufficient delay that the errata was not an issue.  However, it seems like the workaround should be included in the board library clock.c example files to support customization of the board library (where the problem can manifest itself like it did for us).

I just wanted to mention this for your consideration.

Thanks,

Nate