Problems Setting the PLLs on a custom design using GEL files and CCS4

reda38

Expert 1455 points

Other Parts Discussed in Thread: CCSTUDIO

Hello TI staff,

I contact you after several debugging days with the PLL.

On my board ARM CPU is to be run at 270MHz on PLL2 and DDR at 216MHz on PLL1.

I try to run a GEL script before going to UBL coding. I use CCS4 and a XDS100v2 JTAG connector.

First of all I try to use the gel files I found on evm365 and there were errors set in this file. It may be adapted for a first version of DM365 or strangely to a DM355 since some registers were badly mapped, some bits were not existing in the DM365 etc... moreover the PLL setup procedure was wrong or incomplete.

I had also to change the XDS100v2 JTAG timeout to very slow to avoid error messages.

So I took an IPNC gel files which i modified, because there was no OnTarget function. And I added missing parts.

I set the device so that the CLKOUT2 is output on GIO31, for this I set the PINMUX4 register and also the PERI_CLKCTL register to enable the clockout.

My goal was to output this clock2 which is identical to the AEMIF one (in DIV parameters) because I had problems with my NAND. I wanted to verify that the clock out the PLL but before the SYSCLKx dividers was set properly to 432MHz.

The problem is that I cannot see anything on my pin and I am stuck (doubt) with the idea that no clock is working at all and that I cannot verify it.

I tried to print the content of status registers to check and in DCHANGE registers there was 0 on all bits meaning no change had taken part. Maybe it can be a clue to the solution. But at this point I am sure of nothing.

Thank you for your help.

over 15 years ago

0 Tai Nguyen over 15 years ago

TI__Expert 5955 points

Hello,

First, please confirm your board is a custom target board.

It sounds like you are not really to connect the Dm365 with CCS4. Were you able to read/write any registers or memory? I don't have CCS4 installed on my laptop so I can verify how it looks if the DM365 is connected or not. I think somewhere in the left corner it says if the processor is connected or not. The first step is to make sure the CCS4 connected to the DM365.

Please let me know if that is the case.

Thanks,

Tai Nguyen

0 reda38 over 15 years ago in reply to Tai Nguyen

Expert 1455 points

Hello Thank you for answering,

I use a target custom board.

I use CCS4.

I can launch a debugger session and connect my jtag to the target. In Eclipse environment, I can read "Connected".

I can read some space in memory.

I can run completely my GEL file. But the results are not in line with expected.

thanks

reda

0 Tai Nguyen over 15 years ago in reply to reda38

TI__Expert 5955 points

Hello,

You said you can read some memory but can you write to and read back from some memory?

Please attached the GEL file you are using and point out which ones do not make sense.

Thanks,

Tai Nguyen

0 reda38 over 15 years ago in reply to Tai Nguyen

Expert 1455 points

Hello Taï

Thank you for replying.

I can read, but i cannot write and then read back what I have written.

I copy the gel file I use (cause the attach media function does not work properly).

thank you for your help.

-------------------------------------------------------------------------------

/* ------------------------------------------------------------------------ *
*                                                                          *
* dm365_gel_for_TI_support.gel                                           *
* CCStudio 4.0+ and the DM365 based gel.                                  *
*                                                                          *
* ------------------------------------------------------------------------ */

/* ------------------------------------------------------------------------ *
*                                                                          *
* StartUp( )                                                              *
*      Setup Memory Map                                                    *
*                                                                          *
* ------------------------------------------------------------------------ */
StartUp( )
{
    Setup_Memory_Map( );
}

/* ------------------------------------------------------------------------ *
*                                                                          *
* Device System Controller                                                *
*                                                                          *
* ------------------------------------------------------------------------ */
#define SYSTEM_BASE         0x01C40000
#define PINMUX0             *( unsigned int* )( SYSTEM_BASE + 0x00 )
#define PINMUX1             *( unsigned int* )( SYSTEM_BASE + 0x04 )
#define PINMUX2             *( unsigned int* )( SYSTEM_BASE + 0x08 )
#define PINMUX3             *( unsigned int* )( SYSTEM_BASE + 0x0C )
#define PINMUX4             *( unsigned int* )( SYSTEM_BASE + 0x10 )
#define BOOTCFG             *( unsigned int* )( SYSTEM_BASE + 0x14 )
#define ARM_INTMUX          *( unsigned int* )( SYSTEM_BASE + 0x18 )
#define EDMA_INTMUX         *( unsigned int* )( SYSTEM_BASE + 0x1C )
#define DDR_SLEW            *( unsigned int* )( SYSTEM_BASE + 0x20 )
#define UHPI_CTL            *( unsigned int* )( SYSTEM_BASE + 0x24 )
#define DEVICE_ID           *( unsigned int* )( SYSTEM_BASE + 0x28 )
#define VDAC_CONFIG         *( unsigned int* )( SYSTEM_BASE + 0x2C )
#define TIMER64_CTL         *( unsigned int* )( SYSTEM_BASE + 0x30 )
#define USBPHY_CTL          *( unsigned int* )( SYSTEM_BASE + 0x34 )
#define MISC                *( unsigned int* )( SYSTEM_BASE + 0x38 )
#define MSTPRI0             *( unsigned int* )( SYSTEM_BASE + 0x3C )
#define MSTPRI1             *( unsigned int* )( SYSTEM_BASE + 0x40 )
#define VPSS_CLKCTL         *( unsigned int* )( SYSTEM_BASE + 0x44 )
#define PERI_CLKCTL         *( unsigned int* )( SYSTEM_BASE + 0x48 )
#define DEEPSLEEP           *( unsigned int* )( SYSTEM_BASE + 0x4C )
#define DFT_ENABLE          *( unsigned int* )( SYSTEM_BASE + 0x50 )
#define DEBOUNCE0           *( unsigned int* )( SYSTEM_BASE + 0x54 )
#define DEBOUNCE1           *( unsigned int* )( SYSTEM_BASE + 0x58 )
#define DEBOUNCE2           *( unsigned int* )( SYSTEM_BASE + 0x5C )
#define DEBOUNCE3           *( unsigned int* )( SYSTEM_BASE + 0x60 )
#define DEBOUNCE4           *( unsigned int* )( SYSTEM_BASE + 0x64 )
#define DEBOUNCE5           *( unsigned int* )( SYSTEM_BASE + 0x68 )
#define DEBOUNCE6           *( unsigned int* )( SYSTEM_BASE + 0x6C )
#define DEBOUNCE7           *( unsigned int* )( SYSTEM_BASE + 0x70 )
#define VTPIO_CTL           *( unsigned int* )( SYSTEM_BASE + 0x74 )
#define PUPDCTL0            *( unsigned int* )( SYSTEM_BASE + 0x78 )
#define PUPDCTL1            *( unsigned int* )( SYSTEM_BASE + 0x7C )
#define HDIMCOBT            *( unsigned int* )( SYSTEM_BASE + 0x80 )
#define PLL0_CONFIG         *( unsigned int* )( SYSTEM_BASE + 0x84 )
#define PLL1_CONFIG         *( unsigned int* )( SYSTEM_BASE + 0x88 )

#define GPINT_GPEN            (unsigned int *) 0x01C21C08
#define GPTDAT_GPDIR        (unsigned int *) 0x01C21C0C

#define PSC_PTCMD           *( unsigned int* )( 0x01c41120 )
#define PSC_PTSTAT          *( unsigned int* )( 0x01c41128 )

#define    DDR_BASE_ADDR         0x80000000

#define    AEMIF_CE0_BASE_ADDR 0x02000000
#define    AEMIF_CE1_BASE_ADDR 0x04000000

OnResetDetected()
{
    GEL_TextOut( "\nReset Detected - Reinitializing\n\n");
    OnTargetConnect();
}

/* ------------------------------------------------------------------------ *
*                                                                          *
* OnTargetConnect( )                                                      *
*      Setup PinMux, Power, PLLs, DDR, & EMIF                              *
*                                                                          *
* ------------------------------------------------------------------------ */
OnTargetConnect( )
{
    GEL_TextOut( "\nDM365 ARM Startup Sequence\n\n" );

    Setup_Memory_Map();

    if ((*((unsigned int *)0x01C408E4)&3) != 0)    // Only initialize on cold boot (RSTYPE field)
    {
        //This block of code implements the VPSS Sync Reset Fix
        GEL_TextOut("VPSS Sync Reset Fix\n");
        VPSS_CLKCTL = 0x80;

        psc_change_state( 47 , 0 );
        psc_change_state( 47 , 1 );
        *GPINT_GPEN = 0x00020000;
        *GPTDAT_GPDIR = 0x00020002;
        GEL_TextOut("VPSS Sync Reset Fix DONE\n");
    }

    PERI_CLKCTL = 0x243F0FFB;   // Peripheral Clock control - validate ARM on PLL2 - CLKOUT2 out enable=pll1_sysclk9
    GEL_TextOut("PERI_CLKCTL Setting DONE\n");

    Disable_IRQ_Flush_Cache();         // Clean up system state
    Setup_Psc_All_On();
    Setup_Pin_Mux();                   // Setup Pin Mux
    PLLInit_24M_PLL2arm270_PLL1ddr216(); //Setup PLL 1 and 2
    Setup_DDR2();                      // Configure DDR2 controller
    Setup_AEMIF();                     // Setup AEMIF (CE0)

    GEL_TextOut( "\nStartup Complete.\n\n" );
}

/* ------------------------------------------------------------------------ *
*                                                                          *
* OnPreFileLoaded( )                                                      *
*      This function is called automatically when the 'Load Program'       *
*      Menu item is selected.                                              *
*                                                                          *
* ------------------------------------------------------------------------ */
OnPreFileLoaded( )
{
    /*
     * GEL_Reset() is used to deal with the worst case senario of
     * unknown target state. If for some reason a reset is not desired
     * upon target connection, GEL_Reset() may be removed and replaced
     * with something "less brutal" like a cache initialization
     * function.
     */
    GEL_Reset();

    Disable_VPSS( );                    // Disable VPSS
    Disable_IRQ_Flush_Cache( );         // Clean up system state
    Disable_EDMA( );                    // Disable EDMA

    GEL_TextOut( "\n" );
}

/* ------------------------------------------------------------------------ *
*                                                                          *
* OnRestart( )                                                            *
*      This function is called by CCS when you do Debug->Restart.          *
*      The goal is to put the C6x into a known good state with respect to *
*      cache, edma and interrupts.                                         *
*      Failure to do this can cause problems when you restart and          *
*      run your application code multiple times. This is different        *
*      then OnPreFileLoaded() which will do a GEL_Reset() to get the       *
*      C6x into a known good state.                                        *
*                                                                          *
* ------------------------------------------------------------------------ */
OnRestart( int nErrorCode )
{
//    Disable_IRQ_Flush_Cache( );         // Clean up system state
//    Disable_EDMA( );                    // Disable EDMA

    GEL_TextOut( "\n" );
}

menuitem "DM365 Memory Map";

/* ------------------------------------------------------------------------ *
*                                                                          *
* Setup_Memory_Map( )                                                     *
*      Setup the Memory Map for ARM side only.                             *
*                                                                          *
* ------------------------------------------------------------------------ */
hotmenu
Setup_Memory_Map( )
{
    GEL_MapOn( );
    GEL_MapReset( );

    /* ARM RAM & ROM */
    GEL_MapAddStr( 0x00000000, 0, 0x00004000, "R|W|AS4", 0 );   // ARM RAM0 Instruction
    GEL_MapAddStr( 0x00004000, 0, 0x00004000, "R|W|AS4", 0 );   // ARM RAM1 Instruction
    GEL_MapAddStr( 0x00008000, 0, 0x00004000, "R|AS4",   0 );   // ARM ROM Instruction
    GEL_MapAddStr( 0x00010000, 0, 0x00004000, "R|W|AS4", 0 );   // ARM RAM0 Data
    GEL_MapAddStr( 0x00014000, 0, 0x00004000, "R|W|AS4", 0 );   // ARM RAM1 Data
    GEL_MapAddStr( 0x00018000, 0, 0x00004000, "R|AS4",   0 );   // ARM ROM Data

    /* Extend Trace */
    GEL_MapAddStr( 0x01BC0000, 0, 0x00001900, "R|W|AS4", 0 );   // ARM ETB

    /* Peripherals */
    GEL_MapAddStr( 0x01C00000, 0, 0x00000644, "R|W|AS4", 0 );   // EDMA Channel Ctrl
    GEL_MapAddStr( 0x01C01000, 0, 0x00000098, "R|W|AS4", 0 );   // EDMA Channel Ctrl
    GEL_MapAddStr( 0x01C02000, 0, 0x00000098, "R|W|AS4", 0 );   // EDMA Channel Ctrl
    GEL_MapAddStr( 0x01C02200, 0, 0x00000098, "R|W|AS4", 0 );   // EDMA Channel Ctrl

    GEL_MapAddStr( 0x01C10000, 0, 0x00000400, "R|W|AS4", 0 );   // EDMA Transfer Ctrl 0

    GEL_MapAddStr( 0x01C10400, 0, 0x00000400, "R|W|AS4", 0 );   // EDMA Transfer Ctrl 1

    GEL_MapAddStr( 0x01C10800, 0, 0x00000400, "R|W|AS4", 0 );   // EDMA Transfer Ctrl 2

    GEL_MapAddStr( 0x01C10C00, 0, 0x00000400, "R|W|AS4", 0 );   // EDMA Transfer Ctrl 3

    GEL_MapAddStr( 0x01C20000, 0, 0x00000400, "R|W|AS4", 0 );   // UART 0
    GEL_MapAddStr( 0x01C20800, 0, 0x00000400, "R|W|AS4", 0 );   // Timer 3
    GEL_MapAddStr( 0x01C20C00, 0, 0x00000400, "R|W|AS4", 0 );   // RTO
    GEL_MapAddStr( 0x01C21000, 0, 0x00000400, "R|W|AS4", 0 );   // I2C
    GEL_MapAddStr( 0x01C21400, 0, 0x00000400, "R|W|AS4", 0 );   // Timer 0
    GEL_MapAddStr( 0x01C21800, 0, 0x00000400, "R|W|AS4", 0 );   // Timer 1
    GEL_MapAddStr( 0x01C21C00, 0, 0x00000400, "R|W|AS4", 0 );   // Timer 2 / WDT
    GEL_MapAddStr( 0x01C22000, 0, 0x00000400, "R|W|AS4", 0 );   // PWM 0
    GEL_MapAddStr( 0x01C22400, 0, 0x00000400, "R|W|AS4", 0 );   // PWM 1
    GEL_MapAddStr( 0x01C22800, 0, 0x00000400, "R|W|AS4", 0 );   // PWM 2
    GEL_MapAddStr( 0x01C22C00, 0, 0x00000400, "R|W|AS4", 0 );   // PWM 3
    GEL_MapAddStr( 0x01C23000, 0, 0x00000800, "R|W|AS4", 0 );   // SPI4
    GEL_MapAddStr( 0x01C23800, 0, 0x00000400, "R|W|AS4", 0 );   // Timer 4
    GEL_MapAddStr( 0x01C23C00, 0, 0x00000400, "R|W|AS4", 0 );   // A/D Converter Interface
    GEL_MapAddStr( 0x01C40000, 0, 0x00000800, "R|W|AS4", 0 );   // System Module
    GEL_MapAddStr( 0x01C40800, 0, 0x00000400, "R|W|AS4", 0 );   // PLL 1
    GEL_MapAddStr( 0x01C40C00, 0, 0x00000400, "R|W|AS4", 0 );   // PLL 2
    GEL_MapAddStr( 0x01C41000, 0, 0x00001000, "R|W|AS4", 0 );   // PSC Domain Control
    GEL_MapAddStr( 0x01C48000, 0, 0x00000400, "R|W|AS4", 0 );   // ARM Interrupts
    GEL_MapAddStr( 0x01C64000, 0, 0x00002000, "R|W|AS4", 0 );   // USB 2.0 + RAM
    GEL_MapAddStr( 0x01C66000, 0, 0x00000800, "R|W|AS4", 0 );   // SPI0
    GEL_MapAddStr( 0x01C66800, 0, 0x00000800, "R|W|AS4", 0 );   // SPI1
    GEL_MapAddStr( 0x01C67000, 0, 0x00000800, "R|W|AS4", 0 );   // GPIO
    GEL_MapAddStr( 0x01C67800, 0, 0x00000800, "R|W|AS4", 0 );   // SPI2
    GEL_MapAddStr( 0x01C68000, 0, 0x00000800, "R|W|AS4", 0 );   // SPI3
    GEL_MapAddStr( 0x01C69000, 0, 0x00000400, "R|W|AS4", 0 );   // RTC (Real time clk)
    GEL_MapAddStr( 0x01C69400, 0, 0x00000400, "R|W|AS4", 0 );   // Keyscan
    GEL_MapAddStr( 0x01C69800, 0, 0x00000800, "R|W|AS4", 0 );   // UHPI (Universal Host Port Interface)

    GEL_MapAddStr( 0x01C70000, 0, 0x00000100, "R|W|AS4", 0 );   // VPSS - ISP System Configuration Registers
    GEL_MapAddStr( 0x01C70200, 0, 0x00000100, "R|W|AS4", 0 );   // VPSS - VPBE Clock Control Register
    GEL_MapAddStr( 0x01C70400, 0, 0x00000400, "R|W|AS4", 0 );   // VPSS - Resizer Registers
    GEL_MapAddStr( 0x01C70800, 0, 0x00000800, "R|W|AS4", 0 );   // VPSS - IPIPE Registers
    GEL_MapAddStr( 0x01C71000, 0, 0x00000200, "R|W|AS4", 0 );   // VPSS - ISIF Registers
    GEL_MapAddStr( 0x01C71200, 0, 0x00000200, "R|W|AS4", 0 );   // VPSS - IPIPEIF Registers
    GEL_MapAddStr( 0x01C71400, 0, 0x00000100, "R|W|AS4", 0 );   // VPSS - H3A Registers
    GEL_MapAddStr( 0x01C71800, 0, 0x00000400, "R|W|AS4", 0 );   // VPSS - Face Detect IF Registers
    GEL_MapAddStr( 0x01C71C00, 0, 0x00000100, "R|W|AS4", 0 );   // VPSS - OSD Registers
    GEL_MapAddStr( 0x01C71E00, 0, 0x00000200, "R|W|AS4", 0 );   // VPSS - VENC Registers

    GEL_MapAddStr( 0x01D00000, 0, 0x00002000, "R|W|AS4", 0 );   // MMC / SD1
    GEL_MapAddStr( 0x01D02000, 0, 0x00002000, "R|W|AS4", 0 );   // McBSP
    GEL_MapAddStr( 0x01D06000, 0, 0x00000400, "R|W|AS4", 0 );   // UART 1
    GEL_MapAddStr( 0x01D07000, 0, 0x00001000, "R|W|AS4", 0 );   // EMAC Control Regs
    GEL_MapAddStr( 0x01D08000, 0, 0x00002000, "R|W|AS4", 0 );   // EMAC Control Module RAM
    GEL_MapAddStr( 0x01D0A000, 0, 0x00001000, "R|W|AS4", 0 );   // EMAC Control Module Regs
    GEL_MapAddStr( 0x01D0B000, 0, 0x00000800, "R|W|AS4", 0 );   // EMAC MDIO

    GEL_MapAddStr( 0x01D0C000, 0, 0x00000400, "R|W|AS4", 0 );   // VoiceCodec
    GEL_MapAddStr( 0x01D10000, 0, 0x00001000, "R|W|AS4", 0 );   // ASYNC EMIF Control
    GEL_MapAddStr( 0x01D11000, 0, 0x0000F000, "R|W|AS4", 0 );   // MMC / SD0

    GEL_MapAddStr( 0x02000000, 0, 0x02000000, "R|W|AS4", 0 );   // ASYNC EMIF DATA CE0
    GEL_MapAddStr( 0x04000000, 0, 0x02000000, "R|W|AS4", 0 );   // ASYNC EMIF DATA CE1

    GEL_MapAddStr( 0x11F00000, 0, 0x00020000, "R|W|AS4", 0 );   // MJCP DMA Port
    GEL_MapAddStr( 0x12000000, 0, 0x00080000, "R|W|AS4", 0 );   // HDVICP DMA Port

    GEL_MapAddStr( 0x20000000, 0, 0x00008000, "R|W|AS4", 0 );   // DDR2 Control Registers
    GEL_MapAddStr( 0x80000000, 0, 0x10000000, "R|W|AS4", 0 );   // DDR2 SDRAM EMIF
}

/* ------------------------------------------------------------------------ *
*                                                                          *
* Clear_Memory_Map( )                                                     *
*      Clear the Memory Map                                                *
*                                                                          *
* ------------------------------------------------------------------------ */
hotmenu
Clear_Memory_Map( )
{
    GEL_MapOff( );
    GEL_MapReset( );
}

menuitem "DM365 Functions";

/* ------------------------------------------------------------------------ *
*                                                                          *
* Flush_Cache_Disable_MMU( )                                              *
*      Flush Cache & Disable MMU                                           *
*                                                                          *
* ------------------------------------------------------------------------ */
Disable_IRQ_Flush_Cache( )
{
    #define INTC_FIQ0            *( int* )( 0x01c48000 )
    #define INTC_FIQ1            *( int* )( 0x01c48004 )
    #define INTC_IRQ0            *( int* )( 0x01c48008 )
    #define INTC_IRQ1            *( int* )( 0x01c4800c )
    #define INTC_EINT0           *( int* )( 0x01c48018 )
    #define INTC_EINT1           *( int* )( 0x01c4801c )
    #define INTC_INTCTL          *( int* )( 0x01c48020 )
    #define INTC_EABASE          *( int* )( 0x01c48024 )

    GEL_TextOut( "Disable IRQ/FIQ\n" );
    CPSR = 0x400000D3;                  // Set to supervisor mode, disable IRQ/FIQ

    GEL_TextOut( "Flush Cache\n" );
    REG_CP15_FLSH_DI;                   // Flush then disable D-Cache & I-Cache
    REG_CP15_I_CACHE = 1;
    REG_CP15_D_CACHE = 1;

    GEL_TextOut( "Disable MMU\n" );
    REG_CP15_MMU = 0;                   // Disable MMU

    INTC_INTCTL = 4;                    // Disable ARM interrupts
    INTC_EABASE = 0;
    INTC_EINT0 = 0;
    INTC_EINT1 = 0;

    INTC_FIQ0 = 0xffffffff;
    INTC_FIQ1 = 0xffffffff;
    INTC_IRQ0 = 0xffffffff;
    INTC_IRQ1 = 0xffffffff;

    _wait( 200 );
}

/* ------------------------------------------------------------------------ *
*                                                                          *
* Disable_VPSS( )                                                         *
*      Disable VPFE & VPBE                                                 *
*                                                                          *
* ------------------------------------------------------------------------ */
Disable_VPSS( )
{
    #define ISIF_SYNCEN         *( unsigned int* )( 0x01C71000 )
    #define VPBE_PCR            *( unsigned int* )( 0x01C72704 )
    #define VPBE_VENC_VMOD      *( unsigned int* )( 0x01C72400 )
    #define VPBE_OSD_MODE       *( unsigned int* )( 0x01C72600 )

    GEL_TextOut( "Disable VPSS\n" );

    ISIF_SYNCEN = 0;              // Disable VPFE
}

/* ------------------------------------------------------------------------ *
*                                                                          *
* Disable_EDMA( )                                                         *
*      Disabe EDMA events and interrupts, clear any pending events         *
*                                                                          *
* ------------------------------------------------------------------------ */
Disable_EDMA( )
{
    #define EDMA_3CC_IECRH          *( int* )( 0x01C0105C )
    #define EDMA_3CC_EECRH          *( int* )( 0x01C0102C )
    #define EDMA_3CC_ICRH           *( int* )( 0x01C01074 )
    #define EDMA_3CC_ECRH           *( int* )( 0x01C0100C )

    #define EDMA_3CC_IECR           *( int* )( 0x01C01058 )
    #define EDMA_3CC_EECR           *( int* )( 0x01C01028 )
    #define EDMA_3CC_ICR            *( int* )( 0x01C01070 )
    #define EDMA_3CC_ECR            *( int* )( 0x01C01008 )

    GEL_TextOut( "Disable EDMA events\n" );
    EDMA_3CC_IECRH = 0xFFFFFFFF;   // IERH ( disable high interrupts )
    EDMA_3CC_EECRH = 0xFFFFFFFF;   // EERH ( disable high events )
    EDMA_3CC_ICRH   = 0xFFFFFFFF;   // ICRH ( clear high interrupts )
    EDMA_3CC_ECRH   = 0xFFFFFFFF;   // ICRH ( clear high events )

    EDMA_3CC_IECR   = 0xFFFFFFFF;   // IER ( disable low interrupts )
    EDMA_3CC_EECR   = 0xFFFFFFFF;   // EER ( disable low events )
    EDMA_3CC_ICR    = 0xFFFFFFFF;   // ICR ( clear low interrupts )
    EDMA_3CC_ECR    = 0xFFFFFFFF;   // ICRH ( clear low events )
}

/* ------------------------------------------------------------------------ *
*                                                                          *
* Setup_Pin_Mux( )                                                        *
*      Configure Pin Multiplexing                                          *
*                                                                          *
* ------------------------------------------------------------------------ */
Setup_Pin_Mux( )
{
    GEL_TextOut( "Setup PinMux for v1... " );

    PINMUX0 = 0x00FD4355; // MMC/SD0, McBSP, MMC/SD1, VPFE In Y, GIO100-103
    PINMUX1 = 0x28555555; // VPBE LCD
    PINMUX2 = 0x00001900; // GIO50-51, GIO57-78, AEMIF 8 bit Flash
    PINMUX3 = 0x375AFFFF; // GIO26, SPI0, I2C, UART0, EMAC
    //PINMUX4 = 0x55603CFF; // MMC/SD1, McBSP, VPBE LCD, GIO31 ,34-36
    PINMUX4 = 0x55603FFF; // MMC/SD1, McBSP, VPBE LCD, CLKOUT2 ,34-36

    GEL_TextOut( "PinMux Done\n" );
}

/* ------------------------------------------------------------------------ *
*                                                                          *
* Setup_Psc_All_On( )                                                     *
*      Enable all non-reserved power modules.                              *
*                                                                          *
* ------------------------------------------------------------------------ */
Setup_Psc_All_On( )
{

unsigned char i=0;
unsigned char lpsc_start;
unsigned char lpsc_end,lpscgroup,lpscmin,lpscmax;

lpscmin =0;
lpscmax =3;

GEL_TextOut( "Setup Power Modules (All on)... " );

for(lpscgroup=lpscmin ; lpscgroup <=lpscmax; lpscgroup++)
{
    if(lpscgroup==0)
    {
        lpsc_start = 0; // Enabling LPSC 0 to 15 SCR first
        lpsc_end   = 15;
    }
    else if(lpscgroup==1)
    {/* Skip reserved LPSCs 16 */
        lpsc_start = 17; // Enabling LPSC 17 to 28 SCR first
        lpsc_end   = 28;
    }
    else if (lpscgroup == 2)
    { /* Skip locked =(Always on or reserved) LPSCs [29-37] */
        lpsc_start = 38;
        lpsc_end   = 47;
    }
    else
    {
        lpsc_start = 50;
        lpsc_end   = 51;
    }

    //state=0x3=Enable LPSC's
    for(i=lpsc_start; i<=lpsc_end; i++)
    {
           GEL_TextOut( "Module i= %d... ",,,,,i );
        psc_change_state( i , 3 );
    }
}

GEL_TextOut("\nDM365 all Module Clocks are Turned on\n");
}

/* ------------------------------------------------------------------------ *
*                                                                          *
* psc_change_state( id, state )                                           *
*      id    = Domain #ID                                                  *
*      state = ( ENABLE, DISABLE, SYNCRESET, RESET )                       *
*              (   =3 ,   =2   ,    =1    ,   =0 )                       *
*                                                                          *
* ------------------------------------------------------------------------ */
psc_change_state( int id, int state )
{

    int* mdstat                 = ( int* )( 0x01c41800 + ( 4 * id ) );
    int* mdctl                  = ( int* )( 0x01c41a00 + ( 4 * id ) );
    int set_interrupt;

    /*
     * Step 0 - Ignore request if the state is already set as is
     */
    if ( ( ( *mdstat ) & 0x1f ) == state )
        return;

    /*
     * Step 1 - Wait for PTSTAT.GOSTAT to clear
     */
    while( PSC_PTSTAT & 1 );

    /*
     * Step 2 - Set MDCTLx.NEXT to new state
     */
    *mdctl &= ~0x1f;
    *mdctl |= state;

    /*
     * Step 3 - Start power transition ( set PTCMD.GO to 1 )
     */
    PSC_PTCMD |= 1;

    /*
     * Step 4 - Wait for PTSTAT.GOSTAT to clear
     */
    while( PSC_PTSTAT & 1 );

    /*
     * Step 5 - Wait for MDSTAT to be set to requested state
     */
    while ( (*mdstat)&0x1f != state );
}

_wait( int delay )
{
    int i;
    for( i = 0 ; i < delay ; i++ ){}
}

Setup_PLL1()
{
    //-------------------------------------------------
    //Setup PLL1:432Mhz
    //      InpClk:24Mhz
    //-------------------------------------------------

    /* PLL1 base address */
    #define PLL1_BASE            0x01C40800
    #define PLL1_PLLCTL         *(unsigned int *)(PLL1_BASE+ 0x100)
    #define PLL1_OCSEL             *(unsigned int *)(PLL1_BASE+ 0x104)
    #define PLL1_SECCTL         *(unsigned int *)(PLL1_BASE+ 0x108)
    #define PLL1_PLLM             *(unsigned int *)(PLL1_BASE+ 0x110)
    #define PLL1_PREDIV         *(unsigned int *)(PLL1_BASE+ 0x114)
    #define PLL1_PLLDIV1         *(unsigned int *)(PLL1_BASE+ 0x118)
    #define PLL1_PLLDIV2        *(unsigned int *)(PLL1_BASE+ 0x11C)
    #define PLL1_PLLDIV3        *(unsigned int *)(PLL1_BASE+ 0x120)
    #define PLL1_OSCDIV1         *(unsigned int *)(PLL1_BASE+ 0x124)
    #define PLL1_POSTDIV         *(unsigned int *)(PLL1_BASE+ 0x128)
    #define PLL1_BPDIV           *(unsigned int *)(PLL1_BASE+ 0x12C)
    #define PLL1_PLLCMD            *(unsigned int *)(PLL1_BASE+ 0x138)
    #define PLL1_PLLSTAT        *(unsigned int *)(PLL1_BASE+ 0x13C)
    #define PLL1_ALNCTL             *(unsigned int *)(PLL1_BASE+ 0x140)
    #define PLL1_DCHANGE        *(unsigned int *)(PLL1_BASE+ 0x144)
    #define PLL1_CKEN             *(unsigned int *)(PLL1_BASE+ 0x148)
    #define PLL1_SYSTAT            *(unsigned int *)(PLL1_BASE+ 0x150)
    #define PLL1_PLLDIV4        *(unsigned int *)(PLL1_BASE+ 0x160)
    #define PLL1_PLLDIV5        *(unsigned int *)(PLL1_BASE+ 0x164)
    #define PLL1_PLLDIV6        *(unsigned int *)(PLL1_BASE+ 0x168)
    #define PLL1_PLLDIV7        *(unsigned int *)(PLL1_BASE+ 0x16C)
    #define PLL1_PLLDIV8        *(unsigned int *)(PLL1_BASE+ 0x170)
    #define PLL1_PLLDIV9        *(unsigned int *)(PLL1_BASE+ 0x174)


    unsigned int j;
    int    looptimeout;

    GEL_TextOut("Please wait PLL1 initialization is in Progress........\n");

    //Few Steps to perform before the datasheet recommended sequence
    GEL_TextOut("PLL1_PLLCTL at start= %x \n",,,,,PLL1_PLLCTL);

    PLL1_PLLCTL |= 0x00000002;
    GEL_TextOut("PLL Power Down PLL1_PLLCTL after power down= %x \n",,,,,PLL1_PLLCTL);
    for(j=0; j<100; j++) {}

    /*Power up the PLL*/
    PLL1_PLLCTL &= 0xFFFFFFFD;
    GEL_TextOut("PLL Power Up - PLL1_PLLCTL = %x \n",,,,,PLL1_PLLCTL);

    /*Set PLLENSRC '0', PLL Enable(PLLEN) selection */
    PLL1_PLLCTL &= 0xFFFFFFDF;
    GEL_TextOut("PLL ENABLE source selected - PLL1_PLLCTL = %x \n",,,,,PLL1_PLLCTL);

    /*Set PLLEN=0 => PLL BYPASS MODE*/
    PLL1_PLLCTL &= 0xFFFFFFFE;
    GEL_TextOut("PLL Bypass Mode - PLL1_PLLCTL = %x \n",,,,,PLL1_PLLCTL);

    /*Wait at least 4 MXI clock or reference clock cycles to allow PLLEN mux switches properly to bypass clock*/
    for(j=0; j<100; j++) {}

    // PLLRST=1(reset assert)
    PLL1_PLLCTL |= 0x00000008;
    GEL_TextOut("PLL Reset Assert - PLL1_PLLCTL = %x \n",,,,,PLL1_PLLCTL);

    /*Wait at least 5 microseconds*/
    for(j=0; j<10000; j++) {}

    /*Bring PLL out of Reset*/
    PLL1_PLLCTL &= 0xFFFFFFF7;
    GEL_TextOut("PLL Out Reset - PLL1_PLLCTL = %x \n",,,,,PLL1_PLLCTL);

    //Program the Multiplier (M) and Pre-Divider (N1) for PLL1
    PLL1_PLLM   =   0x9;   // VCO will 24*2M/N+1 = 24*2*9/(0+1) = 432Mhz
    PLL1_PREDIV =   0x0;

    GEL_TextOut("PLL Multiplier = %x and PreDivider = %x\n",,,,,PLL1_PLLM,PLL1_PREDIV);

    PLL1_SECCTL = 0x00470000;   // Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 1
    PLL1_SECCTL = 0x00460000;   // Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 0
    PLL1_SECCTL = 0x00400000;   // Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 0
    PLL1_SECCTL = 0x00410000;   // Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 1

    GEL_TextOut("PLL Secondary Control Register Set up\n");

    //Program the PostDiv for PLL1 to divide by 1.
    PLL1_POSTDIV = 0x8000;

    GEL_TextOut("PLL POSTDIV register Set up = %x\n",,,,,PLL1_POSTDIV);

    // Post dividers setting for PLL1
    PLL1_PLLDIV1 = 0x8011;   // POST DIV 432/18 -> USB
    PLL1_PLLDIV3 = 0x8001;   // POST DIV 432/2 -> MJCP/HDVICP
    PLL1_PLLDIV4 = 0x8003;   // POST DIV 432/4 -> EDMA/EDMA CFG
    PLL1_PLLDIV5 = 0x8001;   // POST DIV 432/2 -> VPSS
    PLL1_PLLDIV7 = 0x8000;   // POST DIV 432/1 -> DDR
    PLL1_PLLDIV8 = 0x8003;   // POST DIV 432/4 -> MMC0/SD0
    PLL1_PLLDIV9 = 0x8003;   // POST DIV 432/4 -> CLKOUT

    GEL_TextOut("PLL PostDividers \n");
    GEL_TextOut("PLL POSTDIV 1 register Set up = %x\n",,,,,PLL1_PLLDIV1);
    GEL_TextOut("PLL POSTDIV 3 register Set up = %x\n",,,,,PLL1_PLLDIV3);
    GEL_TextOut("PLL POSTDIV 4 register Set up = %x\n",,,,,PLL1_PLLDIV4);
    GEL_TextOut("PLL POSTDIV 5 register Set up = %x\n",,,,,PLL1_PLLDIV5);
    GEL_TextOut("PLL POSTDIV 7 register Set up = %x\n",,,,,PLL1_PLLDIV7);
    GEL_TextOut("PLL POSTDIV 8 register Set up = %x\n",,,,,PLL1_PLLDIV8);
    GEL_TextOut("PLL POSTDIV 9 register Set up = %x\n",,,,,PLL1_PLLDIV9);

    //Delay
    for(j=0;j<80;j++)
         {
         }

    /*Align all clocks*/
    PLL1_ALNCTL = 0x000001FF;
    GEL_TextOut("PLL1_ALNCTL register Set up = %x\n",,,,,PLL1_ALNCTL);

}

Setup_PLL2()
{
    //-------------------------------------------------
    //Setup PLL2:270Mhz
    //      InpClk:24Mhz
    //      DDR2 :216Mhz
    //-------------------------------------------------

    /* PLL2 base address */
    #define PLL2_BASE            0x01C40C00
    #define PLL2_PLLCTL         *(unsigned int *)(PLL2_BASE+ 0x100)
    #define PLL2_SECCTL         *(unsigned int *)(PLL2_BASE+ 0x108)
    #define PLL2_PLLM             *(unsigned int *)(PLL2_BASE+ 0x110)
    #define PLL2_PREDIV         *(unsigned int *)(PLL2_BASE+ 0x114)
    #define PLL2_PLLDIV1         *(unsigned int *)(PLL2_BASE+ 0x118)
    #define PLL2_PLLDIV2        *(unsigned int *)(PLL2_BASE+ 0x11C)
    #define PLL2_PLLDIV3        *(unsigned int *)(PLL2_BASE+ 0x120)
    #define PLL2_OSCDIV1         *(unsigned int *)(PLL2_BASE+ 0x124)
    #define PLL2_POSTDIV         *(unsigned int *)(PLL2_BASE+ 0x128)
    #define PLL2_BPDIV           *(unsigned int *)(PLL2_BASE+ 0x12C)
    #define PLL2_PLLCMD            *(unsigned int *)(PLL2_BASE+ 0x138)
    #define PLL2_PLLSTAT        *(unsigned int *)(PLL2_BASE+ 0x13C)
    #define PLL2_ALNCTL             *(unsigned int *)(PLL1_BASE+ 0x140)
    #define PLL2_DCHANGE        *(unsigned int *)(PLL1_BASE+ 0x144)
    #define PLL2_CKSTAT            *(unsigned int *)(PLL1_BASE+ 0x14C)
    #define PLL2_SYSTAT            *(unsigned int *)(PLL1_BASE+ 0x150)


    #define PLL2_PLLDIV4        *(unsigned int *)(PLL2_BASE+ 0x160)
    #define PLL2_PLLDIV5        *(unsigned int *)(PLL2_BASE+ 0x164)

    unsigned int j;
    int    looptimeout;

    GEL_TextOut("Please wait PLL2 initialization is in Progress........\n");

    //Few Steps to perform before the datasheet recommended sequence
    GEL_TextOut("PLL2_PLLCTL at start= %x \n",,,,,PLL2_PLLCTL);

    PLL2_PLLCTL |= 0x00000002;
    GEL_TextOut("PLL Power Down PLL2_PLLCTL after power down= %x \n",,,,,PLL2_PLLCTL);
    for(j=0; j<100; j++) {}

    /*Power up the PLL*/
    PLL2_PLLCTL &= 0xFFFFFFFD;
    GEL_TextOut("PLL Power Up - PLL2_PLLCTL = %x \n",,,,,PLL2_PLLCTL);

    /*Set PLLENSRC '0', PLL Enable(PLLEN) selection */
    PLL2_PLLCTL &= 0xFFFFFFDF;
    GEL_TextOut("PLL ENABLE source selected - PLL2_PLLCTL = %x \n",,,,,PLL2_PLLCTL);

    /*Set PLLEN=0 => PLL BYPASS MODE*/
    PLL2_PLLCTL &= 0xFFFFFFFE;
    GEL_TextOut("PLL Bypass Mode - PLL2_PLLCTL = %x \n",,,,,PLL2_PLLCTL);

    /*Wait at least 4 MXI clock or reference clock cycles to allow PLLEN mux switches properly to bypass clock*/
    for(j=0; j<100; j++) {}

    // PLLRST=1(reset assert)
    PLL2_PLLCTL |= 0x00000008;
    GEL_TextOut("PLL Reset Assert - PLL2_PLLCTL = %x \n",,,,,PLL2_PLLCTL);

    /*Wait at least 5 microseconds*/
    for(j=0; j<10000; j++) {}

    /*Bring PLL out of Reset*/
    PLL2_PLLCTL &= 0xFFFFFFF7;
    GEL_TextOut("PLL Out Reset - PLL2_PLLCTL = %x \n",,,,,PLL2_PLLCTL);


    //Program the Multiplier and Pre-Divider for PLL2
    PLL2_PLLM   = 0x2D;   // VCO will 24*2M/N+1 = 270Mhz
    PLL2_PREDIV = 0x7;
    PLL2_POSTDIV = 0x8000;

    PLL2_SECCTL = 0x00470000;   // Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 1
    PLL2_SECCTL = 0x00460000;   // Assert TENABLE = 1, TENABLEDIV = 1, TINITZ = 0
    PLL2_SECCTL = 0x00400000;   // Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 0
    PLL2_SECCTL = 0x00410000;   // Assert TENABLE = 0, TENABLEDIV = 0, TINITZ = 1

    // Post divider setting for PLL2

    PLL2_PLLDIV2 = 0x8000;   // POST DIV 270/1 -> ARM926/ARM968
    PLL2_PLLDIV4 = 0x8003;   // POST DIV 270/4 -> VOICE
    PLL2_PLLDIV5 = 0x8009;   // POST DIV 270/10 -> VENC

    GEL_TextOut("PLL PostDividers \n");
    GEL_TextOut("PLL POSTDIV 2 register Set up = %x\n",,,,,PLL2_PLLDIV2);
    GEL_TextOut("PLL POSTDIV 4 register Set up = %x\n",,,,,PLL2_PLLDIV4);
    GEL_TextOut("PLL POSTDIV 5 register Set up = %x\n",,,,,PLL2_PLLDIV5);

    //Delay
    for(j=0;j<80;j++)
         {
         }

    /*Align all clocks*/
    PLL2_ALNCTL = 0x000001FF;
    GEL_TextOut("PLL2_ALNCTL register Set up = %x\n",,,,,PLL2_ALNCTL);
}

RunPLLs()
{
    int    looptimeout;

    GEL_TextOut("\n****************PLL1 RUN*****************\n");

    /*Set the GOSET bit if a GO operation is not in course*/
    if ((PLL1_PLLSTAT & 0x1)!=0x1)
    {
        PLL1_PLLCMD = 0x00000001; // Go
        GEL_TextOut("PLL GO set \n");

        looptimeout=20;
        while ( ((PLL1_PLLSTAT&0x1) == 0x1) && (looptimeout>0) )
        {
            GEL_TextOut("Waiting for GO operation end \n");
            looptimeout--;
        }

        if (looptimeout==0)
        {
            GEL_TextOut("GO Operation Time Out\n");
            return;
        }

        GEL_TextOut("GO operation endend GOSTAT = %x\n",,,,,PLL1_PLLSTAT&0x1);

        /*Verify that all clocks have changed*/
        GEL_TextOut("PLLDIV Change Status DCHANGE = %x\n",,,,,PLL1_DCHANGE);

        /*Set the CKEN for AUXCLK always be set*/
        PLL1_CKEN |= 0x01;

    }
    else
    {
        GEL_TextOut("Previous GO operation in course. Exiting PLL 1 Run\n");
        return;
    }


    /*Wait for PLL1 to LOCK */
    looptimeout=20;
    while ( ((PLL1_PLLSTAT&0x2) != 0x2) && (looptimeout>0) )
    {
        GEL_TextOut("Waiting for GO operation end \n");
        looptimeout--;
    }

    if (looptimeout==0)
    {
        GEL_TextOut("PLL1 Lock Time Out\n");
        return;
    }
    GEL_TextOut("PLL1 Locked LOCK = %x\n",,,,,PLL1_PLLSTAT&0x2);

    GEL_TextOut("OSCIN STABILITY(0=unstable,1=stable) = %x\n",,,,,PLL1_PLLSTAT&0x4);

    /*Enable the PLL Bit of PLLCTL*/
    PLL1_PLLCTL |= 0x00000001;   // PLLEN=1

    GEL_TextOut("Normal Mode:: PLL1: 432Mhz enabled\n");

    GEL_TextOut("\n****************PLL2 RUN*****************\n");

    /*Set the GOSET bit if a GO operation is not in course*/
    if ((PLL2_PLLSTAT & 0x1)!=0x1)
    {
        PLL2_PLLCMD = 0x00000001; // Go
        GEL_TextOut("PLL2 GO set \n");

        looptimeout=20;
        while ( ((PLL2_PLLSTAT&0x1) == 0x1) && (looptimeout>0) )
        {
            GEL_TextOut("Waiting for GO operation end \n");
            looptimeout--;
        }

        if (looptimeout==0)
        {
            GEL_TextOut("GO Operation Time Out\n");
            return;
        }

        GEL_TextOut("GO operation endend GOSTAT = %x\n",,,,,PLL2_PLLSTAT&0x1);

        /*Verify that all clocks have changed*/
        GEL_TextOut("PLLDIV Change Status DCHANGE = %x\n",,,,,PLL2_DCHANGE);

    }
    else
    {
        GEL_TextOut("Previous GO operation in course. Exiting PLL Setup\n");
        return;
    }

    /*Wait for PLL to LOCK */
    looptimeout=20;
    while ( ((PLL2_PLLSTAT&0x2) != 0x2) && (looptimeout>0) )
    {
        GEL_TextOut("Waiting for GO operation end \n");
        looptimeout--;
    }

    if (looptimeout==0)
    {
        GEL_TextOut("PLL2 Lock Time Out\n");
        return;
    }
    GEL_TextOut("PLL2 Locked LOCK = %x\n",,,,,PLL2_PLLSTAT&0x2);

    GEL_TextOut("OSCIN STABILITY(0=unstable,1=stable) = %x\n",,,,,PLL2_PLLSTAT&0x4);

     //Enable the PLL2
    PLL2_PLLCTL |= 0x00000001;   // PLLEN=1

    GEL_TextOut("Normal Mode:: PLL2: 270Mhz enabled\n");
}

//-------------------------------------------------
//Setup PLL1:432Mhz
//      PLL2:270Mhz
//      InpClk:24Mhz
//      DDR2 :216Mhz
//-------------------------------------------------

PLLInit_24M_PLL2arm270_PLL1ddr216()
{
    Setup_PLL1();
    Setup_PLL2();
    RunPLLs();
}

/* ------------------------------------------------------------------------ *
*                                                                          *
* Setup_DDR2( )                                                           *
* Configure DDR2 to run at 216MHz.                                    *
*                                                                          *
* ------------------------------------------------------------------------ */

#define    DDR_BASE             0x20000000
#define EIDRR                *(unsigned int*)(DDR_BASE + 0x00)            //EMIF Module ID and Revision Register
#define SDSTAT               *(unsigned int*)(DDR_BASE + 0x04)            //SDRAM Status Register
#define SDCFG1               *(unsigned int*)(DDR_BASE + 0x08)             //SDRAM Bank Config Register
#define SDREF                *(unsigned int*)(DDR_BASE + 0x0C)             //SDRAM Refresh Control Register
#define SDTIM0               *(unsigned int*)(DDR_BASE + 0x10)             //SDRAM Timing Register
#define SDTIM1               *(unsigned int*)(DDR_BASE + 0x14)             //SDRAM Timing Register
#define SDCFG2               *(unsigned int*)(DDR_BASE + 0x1C)             //SDRAM Config Register 2
#define VBUSMP               *(unsigned int*)(DDR_BASE + 0x20)             //VBUSM Burst Priority Register
#define VBUSMCFG1            *(unsigned int*)(DDR_BASE + 0x28)             //VBUSM config Value1 Register
#define VBUSMCFG2            *(unsigned int*)(DDR_BASE + 0x2c)             //VBUSM config Value2 Register
#define PERFCNT1             *(unsigned int*)(DDR_BASE + 0x40)            //Performance Counter Register 1
#define PERFCNT2             *(unsigned int*)(DDR_BASE + 0x44)            //Performance Counter Register 2
#define PERFCNTCFG             *(unsigned int*)(DDR_BASE + 0x48)            //Performance Counter Config Register
#define PERFCNTMSTREGSEL     *(unsigned int*)(DDR_BASE + 0x4C)            //Performance Counter Master Region Select Register
#define INTRAW                 *(unsigned int*)(DDR_BASE + 0xC0)            //Interrupt Raw Register
#define INTMASK              *(unsigned int*)(DDR_BASE + 0xC4)            //Interrupt Masked Register
#define INTMASKSET           *(unsigned int*)(DDR_BASE + 0xC8)            //Interrupt Mask Set Register
#define INTMASKCLR           *(unsigned int*)(DDR_BASE + 0xCC)            //Interrupt Mask Clear Register
#define DDRPHYREV            *(unsigned int*)(DDR_BASE + 0xE0)            //DDR PHY ID and Revision Register
#define DDRPHYCTL1           *(unsigned int*)(DDR_BASE + 0xE4)            //DDR PHY Control Register 1
#define DDRPHYCTL2           *(unsigned int*)(DDR_BASE + 0xE8)            //DDR PHY Control Register 2
#define DDR_PHY_VTP_IOCTRL *( unsigned int* )( 0x01C40074 )             // DDR PHY VTP adjust    (Read only)

#define LPSC_DDR_EMIF        13
#define PSC_ADDR             0x01C41000
#define MDSTAT_DDR            *(unsigned int *)(PSC_ADDR+0x800+4*LPSC_DDR_EMIF)
#define MDCTL_DDR            *(unsigned int *)(PSC_ADDR+0xA00+4*LPSC_DDR_EMIF)

//Initializes the DDR2 PHY
//---------------------------------
DDR2_VTP_Init()
{
    // VTP Caliberation
    //PWR_DWN bit is made '0', to power the VTP module

   DDR_PHY_VTP_IOCTRL = DDR_PHY_VTP_IOCTRL & 0xFFFF9F3F;

   // Set bit CLRZ (bit 13)
   DDR_PHY_VTP_IOCTRL = DDR_PHY_VTP_IOCTRL | 0x00002000;

   // Check VTP READY Status
   while( !(DDR_PHY_VTP_IOCTRL & 0x8000));

   // Set bit VTP_IOPWRDWN bit 14 for DDR input buffers)
   // DDR_PHY_VTP_IOCTRL = DDR_PHY_VTP_IOCTRL | 0x00004000;

   // Set bit LOCK(bit7) and PWRSAVE (bit8)
   DDR_PHY_VTP_IOCTRL = DDR_PHY_VTP_IOCTRL | 0x00000080;

   // Powerdown VTP as it is locked (bit 6)
   // Set bit VTP_IOPWRDWN bit 14 for DDR input buffers)
   DDR_PHY_VTP_IOCTRL = DDR_PHY_VTP_IOCTRL | 0x00004040;

    GEL_TextOut("DDR2 VTP Init is done\n");
}

//Setup & Initialize the DDR2 to work at 216Mhz
//-------------------------------------------
DDR16bitInit_216Mhz()
{
   unsigned int j =0,PdNum=0;

    // Config Mode: DDR2
    // Termination: Default
    // ReadLatency: 0x4 (Will taken as 4+1 =5 DDR_CLKP cycles
    // External DQS gatin enabled

    DDRPHYCTL1 = 0x000080C4;
    DDRPHYCTL2    = 0x00000000;



    /*----------------------------DDR CFG----------------------------------------*/
    //Program SDRAM Refresh Control Register
    //Refresh Rate calculated for 216Mhz
    //    *SDREF = 0x00000618;

    //DifferentialDQS: Set
    //DDR2,SDRAM     :Enable
    //Narrow Mode    : Set -16bit DDR2
    //CAS_latency    :0x4
    //Number of Banks:0x8
    //PageSize       :1024 words
    //CE0            :Used

    SDCFG1 = 0x08D34832;
    SDCFG1 = 0x0853C832;

    SDTIM0 = 0x369342D1;
    SDTIM1 = 0x421DC702;

    SDCFG1 = 0x08534832;

    SDREF = 0x00000695;

    //LPSC SyncReset DDR Clock Enable

    MDCTL_DDR = ((MDCTL_DDR & 0xffffffe0) | 0x00000001);

    PSC_PTCMD = (1<<PdNum);

    while(! (((PSC_PTSTAT >> PdNum) & 0x00000001) == 0));

    while(!((MDSTAT_DDR & 0x0000001F) == 0x1));

    GEL_TextOut("DDR_EMIF Controller Sync Reset successful\n");

    //LPSC DDR Clock Enable
    MDCTL_DDR = MDCTL_DDR | 0x3;

    PSC_PTCMD = (1<<PdNum);

    while(! (((PSC_PTSTAT >> PdNum) & 0x00000001) == 0));

    while(!((MDSTAT_DDR & 0x0000001F) == 0x3));

    GEL_TextOut("DDR2 init is done for 16-bit Interface _216Mhz\n");
}

Setup_DDR2( )
{
    DDR2_VTP_Init();
    DDR16bitInit_216Mhz();

}

/* ------------------------------------------------------------------------ *
*                                                                          *
* setup_aemif( )                                                          *
*      Setup Async-EMIF to the specified timings using either NAND HW      *
*      controller or normal EMIF controller                                *
*                                                                          *
* ------------------------------------------------------------------------ */
#define AEMIF_AWCCR             *( unsigned int* )( 0x01d10004 )
#define AEMIF_A1CR              *( unsigned int* )( 0x01d10010 )
#define AEMIF_A2CR              *( unsigned int* )( 0x01d10014 )
#define AEMIF_NANDFCR           *( unsigned int* )( 0x01d10060 )

Setup_AEMIF( )
{
    GEL_TextOut("Setting Up NAND Flash Interface ...\n");
    /* EMIF configuration for NAND mode */
    /* Use extended wait cycles to keep CE low during NAND access */
    AEMIF_AWCCR = 0x000000ff;

    /* Setup CE0 (CS2 NAND)- 8-bit NAND, 9.26ns/cycle */
    // Previous value AEMIF_A1CR = 0x40400204;

    AEMIF_A1CR = 0x40400204;

    //AEMIF_A1CR = 0x4824321C; // SS= Normal Mode, EW=0, WSetup=2, RSetup=3, WStrobe=2,RStrobe=4, WHold=2, RHold=1, TA=3 (9 normalement), 8-bit
    AEMIF_NANDFCR |= 1;
    GEL_TextOut("NAND Flash Interface Setup Done\n");

}

/* ------------------------------------------------------------------------ *
*                                                                          *
*        Few other hotmenus added for DDR + Flash functionality check        *
*                                                                          *
* ------------------------------------------------------------------------ */
/* */

hotmenu DDR_CPU_RW_Verify()
{
    unsigned int i,fail_count;

/* Verify 32 bit read writes */

    fail_count=0;
    GEL_TextOut("Please Wait ...\n");
    for(i=0;i<16;i++)
    *(unsigned int *)(DDR_BASE_ADDR + (i*4)) = ( ((i+4)<<24) + ((i+3)<<16) + ((i+2)<<8) + (i+1) );

    for(i=0;i<16;i++)
    {
        if( (*(unsigned int *)(DDR_BASE_ADDR + (i*4))) != (((i+4)<<24)+((i+3)<<16)+((i+2)<<8)+(i+1)) )
        fail_count++;
    }

    if(fail_count == 0)
         GEL_TextOut("\n DDR CPU 32 bit Read Write Passes ...\n");
    else
         GEL_TextOut("\n DDR CPU 32 bit Read Write Fails ...\n");

/* Verify 16 bit read writes */
    fail_count=0;

    for(i=0;i<16;i++)
    *(unsigned short *)(DDR_BASE_ADDR + (i*2)) = ( ((i+2)<<8) + (i+1) );

    for(i=0;i<16;i++)
    {
        if( (*(unsigned short *)(DDR_BASE_ADDR + (i*2))) != ( ((i+2)<<8) + (i+1) ) )
        fail_count++;
    }

    if(fail_count == 0)
        GEL_TextOut("\n DDR CPU 16 bit Read Write Passes ...\n");
    else
        GEL_TextOut("\n DDR CPU 16 bit Read Write Fails ...\n");

/* Verify 8 bit read writes */
    fail_count=0;

    for(i=0;i<16;i++)
    *(unsigned char *)(DDR_BASE_ADDR + (i*1)) = (i+1);

    for(i=0;i<16;i++)
    {
        if( (*(unsigned char *)(DDR_BASE_ADDR + (i*1))) != (i+1) )
        fail_count++;
    }

    if(fail_count == 0)
        GEL_TextOut("\n DDR CPU 8 bit Read Write Passes ...\n");
    else
        GEL_TextOut("\n DDR CPU 8 bit Read Write Fails ...\n");

}

hotmenu AEMIF_CE0_CPU_RW_Verify()
{
    unsigned int i,fail_count_CE0;

    fail_count_CE0=0;

    for(i=0;i<16;i++)
    *(unsigned int *)(AEMIF_CE0_BASE_ADDR + (i*4)) = ( ((i+4)<<24) + ((i+3)<<16) + ((i+2)<<8) + (i+1) );

    for(i=0;i<16;i++)
    {
        if( (*(unsigned int *)(AEMIF_CE0_BASE_ADDR + (i*4))) != (((i+4)<<24)+((i+3)<<16)+((i+2)<<8)+(i+1)) )
        fail_count_CE0++;
    }

    if(fail_count_CE0 == 0)
         GEL_TextOut("\n AEMIF CE0 CPU Read Write Passes ...\n");
    else
        GEL_TextOut("\n AEMIF CE0 CPU Read Write Fails ...\n");

}

/* ------------------------------------------------------------------------ *
*                                                                          *
*                           Flash functionality check                            *
*                                                                          *
* ------------------------------------------------------------------------ */

#define NANDFLASH_BASE                  0x02000000 // Low CS
#define NANDFLASH_BLOCKS                4096
#define NANDFLASH_PAGESPERBLOCK         64
#define NANDFLASH_PAGES                 (NANDFLASH_BLOCKS * NANDFLASH_PAGESPERBLOCK)
#define NANDFLASH_PAGESIZE              2048
#define NANDFLASH_SPARESIZE             64

#define NANDFLASH_DATA *( unsigned char* )( NANDFLASH_BASE + 0x00 )
#define NANDFLASH_CLE   *( unsigned char* )( NANDFLASH_BASE + 0x10 )
#define NANDFLASH_ALE   *( unsigned char* )( NANDFLASH_BASE + 0x08 )
#define NANDFLASH_FSR   *( unsigned char* )( NANDFLASH_BASE + 0x64 )

#define CMD_READ                    0x00
#define CMD_READID                  0x90
#define CMD_READ_CONFIRM            0x30
#define CMD_PROGRAM                 0x80
#define CMD_PROGRAM_CONFIRM         0x10
#define CMD_ERASE                   0x60
#define CMD_ERASE_CONFIRM           0xD0
#define CMD_STATUS                  0x70
#define CMD_RESET                   0xFF

hotmenu nand_init()
{
    unsigned char mfgid, devid, thirdcycle, fourthcycle, fifthcycle;
    //unsigned char src[NANDFLASH_PAGESIZE + NANDFLASH_SPARESIZE];
    //unsigned char dst[NANDFLASH_PAGESIZE + NANDFLASH_SPARESIZE];

     GEL_TextOut("\n NAND Flash Init ...\n");

    NANDFLASH_CLE = CMD_RESET;
    _wait(100);
     GEL_TextOut("\n NAND Flash Reset Done\n");

    // Start read id operation
    NANDFLASH_CLE = CMD_READID;
    NANDFLASH_ALE = 0x00;

    // Wait for command completion
    _wait(100);
    while((NANDFLASH_FSR & 0x01) == 0);

     GEL_TextOut("\n NAND Flash Read ID Done\n");

    // Get IDs
    mfgid = NANDFLASH_DATA;
    devid = NANDFLASH_DATA;
    thirdcycle = NANDFLASH_DATA;
    fourthcycle = NANDFLASH_DATA;
    fifthcycle = NANDFLASH_DATA;

    GEL_TextOut("\n NAND MFGID = %d\n",,,,,mfgid);
    GEL_TextOut("\n NAND DEVID = %d\n",,,,,devid);
    GEL_TextOut("\n NAND 3rd CYCLE = %d\n",,,,,thirdcycle);
    GEL_TextOut("\n NAND 4th CYCLE = %d\n",,,,,fourthcycle);
    GEL_TextOut("\n NAND 5th CYCLE = %d\n",,,,,fifthcycle);

    //Samsung K9F1G08U0C manufacturer ID     = 0xEC
    //Samsung K9F1G08U0C device ID             = 0xF1

    if (devid != 0xF1)
    {
         GEL_TextOut("\n NAND Flash Wrong Device ID\n");
        return 1;
    }

    return 0;
}
menuitem "DM365 Memories Test";

-------------------------------------------------------------

0 reda38 over 15 years ago in reply to reda38

Expert 1455 points

And here is the Execution Log. As you can see I can execute "few" steps.

(I have just added PLL0 & PLL1 CONFIG registers to double check pll locked bit(s).

----------------------ARM9: GEL Output: DM365 ARM Startup Sequence
ARM9: GEL Output: PERI_CLKCTL Setting DONE
ARM9: GEL Output: Disable IRQ/FIQ
ARM9: GEL Output: Flush Cache
ARM9: GEL Output: Disable MMU
ARM9: GEL Output: Setup Power Modules (All on)...
ARM9: GEL Output: Module i= 0...
ARM9: GEL Output: Module i= 1...
ARM9: GEL Output: Module i= 2...
ARM9: GEL Output: Module i= 3...
ARM9: GEL Output: Module i= 4...
ARM9: GEL Output: Module i= 5...
ARM9: GEL Output: Module i= 6...
ARM9: GEL Output: Module i= 7...
ARM9: GEL Output: Module i= 8...
ARM9: GEL Output: Module i= 9...
ARM9: GEL Output: Module i= 10...
ARM9: GEL Output: Module i= 11...
ARM9: GEL Output: Module i= 12...
ARM9: GEL Output: Module i= 13...
ARM9: GEL Output: Module i= 14...
ARM9: GEL Output: Module i= 15...
ARM9: GEL Output: Module i= 17...
ARM9: GEL Output: Module i= 18...
ARM9: GEL Output: Module i= 19...
ARM9: GEL Output: Module i= 20...
ARM9: GEL Output: Module i= 21...
ARM9: GEL Output: Module i= 22...
ARM9: GEL Output: Module i= 23...
ARM9: GEL Output: Module i= 24...
ARM9: GEL Output: Module i= 25...
ARM9: GEL Output: Module i= 26...
ARM9: GEL Output: Module i= 27...
ARM9: GEL Output: Module i= 28...
ARM9: GEL Output: Module i= 38...
ARM9: GEL Output: Module i= 39...
ARM9: GEL Output: Module i= 40...
ARM9: GEL Output: Module i= 41...
ARM9: GEL Output: Module i= 42...
ARM9: GEL Output: Module i= 43...
ARM9: GEL Output: Module i= 44...
ARM9: GEL Output: Module i= 45...
ARM9: GEL Output: Module i= 46...
ARM9: GEL Output: Module i= 47...
ARM9: GEL Output: Module i= 50...
ARM9: GEL Output: Module i= 51...
ARM9: GEL Output: DM365 all Module Clocks are Turned on
ARM9: GEL Output: Setup PinMux for v1...
ARM9: GEL Output: PinMux Done
ARM9: GEL Output: Please wait PLL1 initialization is in Progress........
ARM9: GEL Output: PLL1_PLLCTL at start= 0x00000051
ARM9: GEL Output: PLL Power Down PLL1_PLLCTL after power down= 0x00000053
ARM9: GEL Output: PLL Power Up - PLL1_PLLCTL = 0x00000051
ARM9: GEL Output: PLL ENABLE source selected - PLL1_PLLCTL = 0x00000051
ARM9: GEL Output: PLL Bypass Mode - PLL1_PLLCTL = 0x00000050
ARM9: GEL Output: PLL Reset Assert - PLL1_PLLCTL = 0x00000058
ARM9: GEL Output: PLL Out Reset - PLL1_PLLCTL = 0x00000050
ARM9: GEL Output: PLL Multiplier = 0x00000009 and PreDivider = 0x00000000
ARM9: GEL Output: PLL Secondary Control Register Set up
ARM9: GEL Output: PLL POSTDIV register Set up = 0x00008000
ARM9: GEL Output: PLL PostDividers
ARM9: GEL Output: PLL POSTDIV 1 register Set up = 0x00008011
ARM9: GEL Output: PLL POSTDIV 3 register Set up = 0x00008001
ARM9: GEL Output: PLL POSTDIV 4 register Set up = 0x00008003
ARM9: GEL Output: PLL POSTDIV 5 register Set up = 0x00008001
ARM9: GEL Output: PLL POSTDIV 7 register Set up = 0x00008000
ARM9: GEL Output: PLL POSTDIV 8 register Set up = 0x00008003
ARM9: GEL Output: PLL POSTDIV 9 register Set up = 0x00008003
ARM9: GEL Output: PLL1_ALNCTL register Set up = 0x000001FF
ARM9: GEL Output: Please wait PLL2 initialization is in Progress........
ARM9: GEL Output: PLL2_PLLCTL at start= 0x00000051
ARM9: GEL Output: PLL Power Down PLL2_PLLCTL after power down= 0x00000053
ARM9: GEL Output: PLL Power Up - PLL2_PLLCTL = 0x00000051
ARM9: GEL Output: PLL ENABLE source selected - PLL2_PLLCTL = 0x00000051
ARM9: GEL Output: PLL Bypass Mode - PLL2_PLLCTL = 0x00000050
ARM9: GEL Output: PLL Reset Assert - PLL2_PLLCTL = 0x00000058
ARM9: GEL Output: PLL Out Reset - PLL2_PLLCTL = 0x00000050
ARM9: GEL Output: PLL PostDividers
ARM9: GEL Output: PLL POSTDIV 2 register Set up = 0x00008000
ARM9: GEL Output: PLL POSTDIV 4 register Set up = 0x00008003
ARM9: GEL Output: PLL POSTDIV 5 register Set up = 0x00008009
ARM9: GEL Output: PLL2_ALNCTL register Set up = 0x000001FF
ARM9: GEL Output: ****************PLL1 RUN*****************
ARM9: GEL Output: PLL GO set
ARM9: GEL Output: GO operation endend GOSTAT = 0x00000000
ARM9: GEL Output: PLLDIV Change Status DCHANGE = 0x00000000
ARM9: GEL Output: PLL1 Locked LOCK = 0x00000002
ARM9: GEL Output: PLL CONFIG REG0 = 0x0E000000
ARM9: GEL Output: OSCIN STABILITY(0=unstable,1=stable) = 0x00000004
ARM9: GEL Output: Normal Mode:: PLL1: 432Mhz enabled
ARM9: GEL Output: ****************PLL2 RUN*****************
ARM9: GEL Output: PLL2 GO set
ARM9: GEL Output: GO operation endend GOSTAT = 0x00000000
ARM9: GEL Output: PLLDIV Change Status DCHANGE = 0x00000000
ARM9: GEL Output: PLL2 Locked LOCK = 0x00000002
ARM9: GEL Output: PLL CONFIG REG1 = 0x0E000000
ARM9: GEL Output: OSCIN STABILITY(0=unstable,1=stable) = 0x00000004
ARM9: GEL Output: Normal Mode: PLL2: 270Mhz enabled
ARM9: GEL Output: DDR2 VTP Init is done
ARM9: GEL Output: DDR_EMIF Controller Sync Reset successful
ARM9: GEL Output: DDR2 init is done for 16-bit Interface _216Mhz
ARM9: GEL Output: Setting Up NAND Flash Interface ...
ARM9: GEL Output: NAND Flash Interface Setup Done
ARM9: GEL Output: Startup Complete.

0 reda38 over 15 years ago in reply to reda38

Expert 1455 points

Hello,

No news about this PLL issue. Did you suceed in getting CLKOUT2 out on a pin ?

cheers

0 reda38 over 15 years ago in reply to reda38

Expert 1455 points

Hello,

I have found other reasons for my NAND not working properly. I open another topic to share my experience.

The problem of not outputing the CLKOUT2 on the alternate GIO31 is still here. DId you find something about it ?

Thank you

0 Tai Nguyen over 15 years ago in reply to reda38

TI__Expert 5955 points

Hello,

I had put together this piece of code in your gel file and tried it on the DM365 EVM. I was able to see both CLKOUT1 on GIO35 (RN3-1) and CLKOUT2 on GIO31 (RN6-3).

Thanks,

-Tai Nguyen

hotmenu Clkout1and2_driver()
{
*(unsigned int *)0x01C40048 &= 0xFFFFFFF9; // Enable CLKOUT2 and CLKOUT1 driver
*(unsigned int *)0x01C40010 |= 0x00030300; // CLKOUT1 -> GIO35 CLKOUT2 -> GIO31
*(unsigned int *)0x01C40D48 |= 0x2; // PLLC2 OBS CLK (CLKOU1) enabled
*(unsigned int *)0x01C40D04 = 0x00; // Oscillator divider output enabled
*(unsigned int *)0x01C40D24 = 0x8001; // Expecting 12 Mhz clock
*(unsigned int *)0x01C40948 |= 0x2; // PLLC1 OBS CLK (CLKOUT2) enabled
*(unsigned int *)0x01C40904 = 0x00; // Oscillator divider output enabled
*(unsigned int *)0x01C40924 = 0x8001; // Expecting 15 Mhz clock
GEL_TextOut(" Clkout 1 and 2 enabled \n");
}

0 reda38 over 15 years ago in reply to Tai Nguyen

Expert 1455 points

Hello Taï.

Thank you for the answer.

What is strange in your answer is tthat you set the OBSCLK Divider enable bit. And it looks like i have misunderstood something or there is a discrepancy with the datasheet.

The OBSCLK is sed for clokout 0 and clokout 1. the clkout 2 is controlled by the sysclk9 and by a divider DIV1. It is not dependent on PLLC1 OBSCLK.

Are you sure of the index ?

Regards

0 Tai Nguyen over 15 years ago in reply to reda38

TI__Expert 5955 points

Hello,

You are correct. For CLKOUT2, it is no need to set the PLLC1 OBSCLK bit.

Regards,

Tai Nguyen

0 reda38 over 15 years ago in reply to Tai Nguyen

Expert 1455 points

Hello again Taï,

and so with these settings you still see CLKOUT2 on GIO31 ?

so my unmodified GEL file would work ? really strange.

regards

0 Tai Nguyen over 15 years ago in reply to reda38

TI__Expert 5955 points

Hello,

It is correct that with these settings I had seen CLKOUT2 on GIO31. I added this piece of code into your GEL file that had the psc_change_state issue corrected and it works fine.

Thanks and regards,

Tai Nguyen

Processors

Processors forum

Problems Setting the PLLs on a custom design using GEL files and CCS4