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RTOS/TMS320C6678: HWI & SWI

Vittorio Argentino
Intellectual 270 points

Part Number: TMS320C6678

Tool/software: TI-RTOS

Hi guy,

someone knows how many HWI is possible to declare for each core on C6678? And how many SWI for each core on C6678?

  • 0
    TI__Guru**** 161600 points
    Hi,

    I've notified the design team. Their feedback will be posted here.

    Best Regards,
    Yordan
  • 0 in reply to Yordan Kovachev
    Intellectual 270 points
    Thank you Yordan.
    I have another question in addition: is it possible to broadcast an event from one core to all others?

    Thanks.
  • 0 in reply to Vittorio Argentino
    TI__Genius 12805 points
    1. Each C66 core has 6 Address Comparators 4 can see either data bus or program bus, 2 sees only program bus. So from the hardware point of view, since there is only single program bus. you can use 6 range comparing. If the compare is equal (==) the architecture limitation is 6
    2. I assume you ask about software break-point using CCS. As far as I know, there is no limitation, but the system needs the ability to modify the instruction (so no ROM code). The implementation of CCS might limit the number of break-points but I never encounter a case like this
    3. It is possible to broadcast an event from one core to all other cores, including itself. But before you do it think about the implications - who clear the interrupt? Can one core clear the interrupt of all other cores? is there a timing race conditions? and so on

    If I answered your questions, please close the thread

    Ran
  • 0 in reply to Vittorio Argentino
    TI__Guru** 116960 points
    C6000 DSP has 12 CPU interrupts(HWI), but 128 possible sources. Users can “tie” any CPU interrupt (numbers 4-15) to any Event ID (0-128). So, interrupt number above means the CPU interrupt number (5 in this case) and Event Id corresponds to the datasheet EVT# as shown.

    I don`t think there is limit on number of SWIs defined for each core in TI RTOS. Each SWI has its own stack so as long as you have the stack, you should be able to generate more SWIs.
  • 0 in reply to ran35366
    Intellectual 270 points

    Hi Ran,
    could you please give me an example of broadcasting (involving your answer number 3)? At the moment, no interest about the secondary implications (who clear the interrupt? Can one core clear the interrupt of all other cores? is there a timing race conditions? etc.)

    Thanks in advance.

  • 0 in reply to Vittorio Argentino
    TI__Genius 12805 points
    I mis-understood your question, so look what Rahul said above.

    If you need more information after reading his answer post again

    Ran
  • 0 in reply to ran35366
    Intellectual 270 points
    Yes, I see the answer after I've sent the question. Thanks. Pending is only the broadcasting example.