Part Number: 66AK2E05
Tool/software: Starterware
Hi to all!
I have a custom board based on K2E_EVM. On my board DDR3 placed directly on PCB, but not on SODIMM,
64-bit, no ECC. Memory chip is MT41J128M16-125 on 1600 MHz. I get latest u-boot source code and compile it with
small change in DDR init only part. (Add two structures with static DDR parameters for my chips). Than I load u-boot.bin
in on chip memory of Cortex-A15 Core 0, at address 0xC000000 as stated in u-boot/boart/ti/k2s_evm/README.
U-boot started, and print init sequence (see below) and go in infinite loop after board_init_f() in hung().
CPU Is working in this moment and I can attach JTAG and connect to Cortex-A15 Core 0 in CCS. I can see DDR3 addresses
from 0x80000000 and other memory. It seems to be correctly working and copy u-boot. But SP register has value 0x0BADCODE.
I don't know how I can debug this issue. Please give me any advise. I can init DDR via gel file from CCS and can fill it some values
in great range. The same parameters I use in u-boot code. And I disable DXEN bit in KS2_DDRPHY_DATX8_8_OFFSET as stated in datasheet.
register.
Here u-boot log:
initcall: 0c03c8e5
U-Boot 2017.01-dirty (Feb 02 2017 - 17:15:42 +0300)
initcall: 0c00d14d
U-Boot code: 0C000000 -> 0C05DD28 BSS: -> 0C0BEB94
initcall: 0c000ff5
CPU: 66AK2Ex SR1.0
initcall: 0c00d591
Model: Texas Instruments Keystone 2 Edison EVM
initcall: 0c00d17d
I2C: ready
initcall: 0c00d16d
DRAM: initcall: 0c001f49
dram_init()
Configure DDR3A from static params.
DDR3 speed 1600
DRAM: 1 GiB
dram_init(): ddr3_size = 1
get_ram_size(): 0x80000000 [0x40000000]
dram_init(): gd->ram_size = 1073741824
initcall: 0c00d339
Monitor len: 000BEB94
Ram size: 40000000
Ram top: C0000000
initcall: 0c00cff9
initcall: 0c00d105
TLB table from bfff0000 to bfff4000
initcall: 0c00d291
initcall: 0c00d0c5
Reserving 762k for U-Boot at: bff31000
initcall: 0c00d0a1
Reserving 33024k for malloc() at: bdef1000
initcall: 0c00d251
Reserving 80 Bytes for Board Info at: bdef0fb0
initcall: 0c00d295
initcall: 0c00d079
Reserving 200 Bytes for Global Data at: bdef0ee8
initcall: 0c00d029
Reserving 26208 Bytes for FDT at: bdeea888
initcall: 0c00d289
initcall: 0c00d3a1
initcall: 0c00d31d
initcall: 0c00d2a1
RAM Configuration:
Bank #0: 80000000 1 GiB
DRAM: 1 GiB
initcall: 0c00d015
New Stack Pointer is: bdeea860
initcall: 0c00d225
initcall: 0c00d1cd
Relocation Offset is: b3f31000
Relocating to bff31000, new gd at bdef0ee8, sp at bdeea860
board_init_f(): Complete!
Here the CCS window after I connect to CPU in this moment:
CCS window screenshot link. Can't attach large image.
here my ddr3 connection
Here my DDR3 settings from u-boot:
u-boot/board/ti/ks2_evm/ddr3_k2e.c
#define DEBUG
#include <common.h>
#include "ddr3_cfg.h"
#include <asm/arch/ddr3.h>
static struct pll_init_data ddr3_400 = DDR3_PLL_400;
static struct pll_init_data ddr3_333 = DDR3_PLL_333;
#ifdef CONFIG_TARGET_SWH101V
extern struct ddr3_phy_config ddr3phy_k2e_1600_2g;
extern struct ddr3_emif_config ddr3emif_k2e_1600_2g;
#endif
u32 ddr3_init(void)
{
struct ddr3_spd_cb spd_cb;
#ifdef CONFIG_TARGET_SWH101V
printf("Configure DDR3A from static params.\n");
spd_cb.ddrspdclock = 1600;
spd_cb.phy_cfg = ddr3phy_k2e_1600_2g;
spd_cb.emif_cfg = ddr3emif_k2e_1600_2g;
spd_cb.ddr_size_gbyte = 1;
#else
if (ddr3_get_dimm_params_from_spd(&spd_cb)) {
printf("Sorry, I don't know how to configure DDR3A.\n"
"Bye :(\n");
for (;;)
;
} else {
printf("Detected SO-DIMM [%s]\n", spd_cb.dimm_name);
}
#endif
Custom files with DDR3 params:
u-boot/board/ti/ks2_evm/ddr3_k2e_cfg.c
#include <common.h>
#include <asm/arch/ddr3.h>
#include "ddr3_cfg.h"
struct ddr3_phy_config ddr3phy_k2e_1600_2g = {
.pllcr = 0x0001C000ul,
.pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
.pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)),
.ptr0 = 0x426213CFul,
.ptr1 = 0xCFC712B3ul,
.ptr2 = 0, /* not set in gel */
.ptr3 = 0x08861A80ul,
.ptr4 = 0x0C827100ul,
.dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
.dcr_val = ((1 << 10)|(1<<27)),
.dtpr0 = 0x011CBB66ul,
.dtpr1 = 0x12840300ul,
.dtpr2 = 0x5002CE00ul,
.mr0 = 0x00001C70ul,
.mr1 = 0x00000006ul,
.mr2 = 0x00000058ul,
.dtcr = 0x710035C7ul,
.pgcr2 = 0x00F07A12ul,
.zq0cr1 = 0x0001007Bul,
.zq1cr1 = 0x0001007Bul,
.zq2cr1 = 0x0001007Bul,
.pir_v1 = 0x00000033ul,
.pir_v2 = 0x0000FF81ul,
};
struct ddr3_emif_config ddr3emif_k2e_1600_2g = {
.sdcfg = 0x6200CE62ul,
.sdtim1 = 0x166C9855ul,
.sdtim2 = 0x00001D4Aul,
.sdtim3 = 0x321DFF53ul,
.sdtim4 = 0x543F07FFul,
.zqcfg = 0x70073200ul,
.sdrfc = 0x00001869ul,
};
If you need and additional info I can provide it. Thank you.
