AM3505: GPMC timing

christophe coutand

Part Number: AM3505

Hi,

I have a AM3505 processor using the GPMC interface to interface a FPGA. I am trying to setup the timing constraints inside the FPGA to match the GPMC configuration. I have a doubt while reading the AM3505 datasheet (http://www.ti.com/product/AM3505/datasheet/timing_requirements_and_switching_characteristics )

In table 6-4, I found all the timing definitions i need but i have a doubt regarding the meaning of the min/max value. For instance, looking at timing F10, assuming H(8)=0, does it means the signal gpmc_noe is stable in a window -2.1 to +2.1 ns around the rising edge of the GPMC clock or does the min and max value have another meaning?

Thanks for any input.

Christophe

over 8 years ago

0 Biser Gatchev-XID over 8 years ago

TI__Guru**** 393215 points

Hi,

Yes, you have understood correctly.

0 christophe coutand over 8 years ago in reply to Biser Gatchev-XID

Prodigy 80 points

Hi Biser,
Thanks for the quick answer. I was afraid that the window defined between the min and max value was actually the unstable zone.
Regards,
Christophe

0 christophe coutand over 8 years ago in reply to Biser Gatchev-XID

Prodigy 80 points

Hi Again Biser,

I have been through all the timing specifications and i have 1 timing specification that still puzzles me which is F15. According to the datasheet, F15 is min (J - 2.1) and max (J+ 1.1). I have J (or GPMC_FCLK) set to 166MHz (6.02ns) and GPMC_CLK set to GPMC_FCLK/2, 12.04ns. With this requirement on the data bus, first, the sampling window on the receive side is fairly small (3.3ns) for a GPMC_CLK of 12.04 ns but also the sampling window is not centered around the rising edge of GPMC_CLK but rather the falling edge. I assume here the min and max value must be interpreted somewhat differently?

Regards,
Christophe

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AM3505: GPMC timing