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TMS320C6678: TSIP TDMU

Hitoshi Sugawara
Mastermind 19970 points
Part Number: TMS320C6678

Hi Folks,

I have a couple of questions about Figure 1-1 TSIP Block Diagram in sprugy4.pdf as follows:

1) Does channel buffer below specify XMT/RCV buffer RAM?
    Page 1-3
    DMA Transfer Control Unit (DMATCU) — The DMATCU initiates the data
transfers between the channel buffers used by the TDMU and the memory buffers used
by the DSP.

2) Does "TDMU channel buffers" in page 1-4 specify XMT/RCV buffer RAM?
3) Does "transmit/receive channel has dual buffers, PING and PONG" in page 2-4 specify XMT/RCV buffer RAM?
4) Does "FIFO memory" in page 2-4 specify XMT/RCV buffer RAM?

5) Could you let me know the memory map addresses of XMT/RCV Context RAM and XMT/RCV Buffer RAM.

Thank you in advance for your kind reply.
Best regards,
Hitoshi

  • 0
    TI__Guru 65405 points
    Hi Hitoshi,

    I've forwarded this to the TSIP experts. Their feedback should be posted here.

    BR
    Tsvetolin Shulev
  • 0 in reply to Cvetolin Shulev-XID
    TI__Guru* 95265 points
    Hi,

    1) Yes, channel buffer in page 1-3 means XMT/RCV buffer RAM used by TDMU.
    2) Yes, TDMU channel buffers in page 1-4 specify XMT/RCV buffer RAM
    3) Yes, transmit/receive channel has dual buffers, PING and PONG in page 2-4 specify XMT/RCV buffer RAM.
    4) Yes, FIFO memory in page 2-4 specify XMT/RCV buffer RAM?
    5) See TABLE 1-1 Memory map for TDMU channel buffers then Table 7-14

    Regards, Eric
  • 0 in reply to lding
    TI__Mastermind 19970 points
    Hi Eric,

    Thank you for your prompt reply.
    Let me clarify one thine about 5) again.
    5) Are XMT/RCV Context RAM and XMT/RCV Buffer RAM located in specified address for TDMU channel buffers?
    Could you please let me konw XMT/RCV conext RAM's start/end addresses and XMT/RCV buffer RAM's start/end addresses?

    Best regards,
    Hitoshi Sugawara
  • 0 in reply to Hitoshi Sugawara
    TI__Guru* 95265 points

    Hi,

    For 5) "XMT/RCV Context RAM and XMT/RCV Buffer RAM" are only shown in Figure 1-1, there is no mentioning Context RAM elsewhere in the documemnt. My understanding of Context RAM is the channel bitmap context which decides if a channel is enabled/disabled in section 2.4. These context registers are at offset 0x8000-0xFFFC from table 1-1.  XMT/RCV buffer RAM registers are at offset 0x10000-0x1FFFC from table 1-1.

    Regards, Eric

      
     

  • 0 in reply to lding
    TI__Mastermind 19970 points
    Hi Eric,

    Thank you!
    I understood.

    Best regards,
    Hitoshi