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RTOS/TMS320C6678: Floating point exception

Part Number: TMS320C6678

Tool/software: TI-RTOS

Hi,

I'm trying to figure it out how the DSP handle
floating point exception, overflow exception and/or
divide by zero exception. I read a lot of documentation
about HWI but  to no vail. I tried to force
the system to divide a generic number by zero or
to force a variable over its size limit but,
misteriously, the system kept working without giving
any evidence of the "problem".

I would like to know if such events are considered
faulty events by the DSP and if it is possible to
catch them somehow.

SDK: v03.02
Code Composer 6.2

  • Giovambattista Astorino said:
    I would like to know if such events are considered
    faulty events by the DSP and if it is possible to
    catch them somehow.

    Math-related status conditions are not considered exceptions on the C6x family of DSPs.  There will be no exception or interrupt generated.  There are status registers to check the result condition of a math operation.  Take a look at http://www.ti.com/lit/ug/sprugh7/sprugh7.pdf, section 2.10 - Control Register File Extensions for Floating-Point Operations.

    That section mentions divide-by-0 detection, but I actually don't see it, maybe you'll have better eyes.

    Regards,

    - Rob

  • Hi Robert,

    Thanks for your answer. One of the "dark spots" was clarified.

    Following your link I've found the proper register connected ,

    for example, to the divide by zero event. Unfortunately the

    main problem is still present. Is there any way to automatically

    detect this kind of event? I've read all the documentation about

    the HWI and it seems that there are no events connected to the

    FAUCR register (divide-by-zero-and-other-math-issue related

    register). Does anyone know if there is a way to map

    these events to an HWI?

  • Giovambattista Astorino said:

    Does anyone know if there is a way to map these events to an HWI?

    I don't know of any way to do that.  That is not an "event" in the architectural sense of the DSP.  DSP Events are mapped for signals either internal or external to the CPU core, and that is not a signal or line in the architecture, at least not that I know of.

    You could try posting to some HW forum, perhaps the "Digital Signal Processors (DSP)" forum, but I suspect that there is no way to get an interrupt or exception upon divide-by-0.  You could point to this thread for reference in your post.

    Regards,

    - Rob

  • I agree with Rob and Astorino

    It looks like there is no way to connect arithmetic fault with interrupt. I looked at table 9.2 of the C66 User Guide www.ti.com/.../sprugw0c.pdf that specifies all the internal (to the core) events. Arithmetic events are not there. (We do not expect external events to be generated by the internal functional units)

    So it looks like the only way to see if event occurred is to periodically checking the values of the fault registers.

    Ran
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