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Linux/AM3352: GPMC_CLK with Sync mode

Kanae
Guru 10085 points
Part Number: AM3352

Tool/software: Linux

Hi Linux support team,

I would like to know how to change the GPMC clock from 50MHz to 100MHz on AM3352 with Linux.
The default setting is 50MHz by Linux kernel version 3.14,
however the maximum GPMC_CLK can be 100MHz.

My customer need to achieve the following status.
-Device: AM3352 (1GHz)
-OS: Linux kernel version 3.14
-GPMC Sync mode (need to change GPMC_CLK from 50MHz to 100MHz)

I am just wondering that there is the limitation for GPMC with sync mode.
Because I found this post, it was very old post and taking other device; DM814x though.

e2e.ti.com/.../678465
 >> All the time GPMC works at GPMC_FCLK = 100MHz
 >> Asynchronous mode: All the Assert/de-assert are done with reference to GPMC_FCLK = 100MHZ
 >> Synchronous mode: All assertions/de-assertions are done with reference to GPMC_CLK = 100MHZ / ( 1+ GPMCFCLKDIVIDER)
 >> Normally in Synchronous mode GPMCFCLKDIVIDER = 0x1 ( GPMC_CLK = GPMC_FCLK/2 = 100MHz/2 = 50 Mhz)

Is the above specs for GPMC on DM814x same as GPMC on Sitara?
I need to explain to my customer about the fastest GPMC_CLK for Synchronous mode on AM335x.
If the fastest GPMC_CLK for Synchronous mode on AM335x is 100MHz,
could I get the advice how to change GPMC_CLK setting in Linux?

Best regards,
Kanae

  • 0
    TI__Guru**** 170625 points

    Hi Kanae,

    It seems like you make no difference between GPMC_FCLK and GPMC_CLK.

    GPMC_FCLK is the GPMC functional clock, this is internal to AM335x clock, source is PRCM, destination is GPMC module.

    GPMC_CLK is the GPMC module output clock on physical pin. Source is GPMC module, destination is external chip. GPMC_CLK can be 100MHz at OPP100. GPMC_CLK freq depends on GPMC_FCLK freq and GPMC module internal settings.

    Regards,
    Pavel

  • 0 in reply to Pavel Botev
    Guru 10085 points


    Hi  Pavel,

    Thank you for your reply.
    I am glad to hear that GPMC_CLK can be 100MHz at OPP100.
    I understand that GPMC_CLK freq depends on GPMC_FCLK freq and GPMC module internal settings.
    -GPMC_FCLK freq : L3S_CLK（CORE_CLKOUTM4 / 2）= GPMC_FCLK=100MHz
    -GPMC_CLK freq : GPMC_FCLK divided by setting number in GPMCFCLKDIVIDER of GPMC_CONFIG1_x Register.

    Operating Performance Points（OPP）has already set "OPP100" as you posted here.
    e2e.ti.com/.../2035153

    However I found the following wiki site.
    processors.wiki.ti.com/.../Tips_for_configuring_OMAP35x,_AM35x,_and_AM-DM37x_GPMC_registers

    There are some rules to configure GPMC register for OMAP35x, AM35x and AM-DM37x.
    Are the rules applied for AM335x?
    If so, sync mode and burst access on AM335x GPMC cannot configure that GPMC_CLK is 100MHz, right?

    Best regards,
    Kanae

  • 0 in reply to Pavel Botev
    Guru 10085 points
    Hi Pavel,

    Thank you for your quick reply!

    Best regards,
    Kanae
  • 0 in reply to Pavel Botev
    Guru 15520 points
    Hi Pavel,

    I'm working with Kanae.

    We want to know how to configure the AM335x GPMC_CLK in the Linux SDK.
    From AM335x TRM, I understand that GPMC_FCLK and GPMC_CLK max frequency are 100MHz.
    And I understand that we can configure GPMC_CLK to 100MHz whether access modes are Async/Sync/single/burst access.
    Is it correct?

    Rule1 of "Rules of Setting up Synchronous Access" in TI wiki page you attached above, it said
    >if your L3 Clock is 166MHz, you have to reduce the GPMC_CLK by setting GPMCFCLKDIVIDER=1 (ie, divide by 2).
    >GPMC_FCLK = 166MHz GPMC_CLK = 83MHz

    I guess this is example for other Sitara/OMAP device , not for AM335x.
    Because in other device's GPMC_FCLK and GPMC_CLK max frequency are different.
    For example OMAP35x GPMC_FCLK max is 166MHz and GPMC_CLK max are 83MHz.

    So, I guess this Rule1 are only trying to say "PAGEBURSTACCESSTIME must be a multiple of GPMCFCLKDIVIDER+1".

    Can you please give us answers for the following questions?
    Q1.Can we cofigure GPMC_CLK to 100MHz whether access modes are Async/Sync/single/burst access?
    Q2.We want to know the procedure of how to configure the GPMC_CLK to 100MHz in the Linux SDK.
    Can you please give us an advice?

    best regards,
    g.f.
  • 0 in reply to g.f.
    TI__Guru**** 170625 points

    g.f. said:
    And I understand that we can configure GPMC_CLK to 100MHz whether access modes are Async/Sync/single/burst access.
    Is it correct?

    Yes, it is. Note that in async mode (NAND mode), GPMC_CLK is not propagated outside the AM335x device.

    g.f. said:
    Rule1 of "Rules of Setting up Synchronous Access" in TI wiki page you attached above, it said
    >if your L3 Clock is 166MHz, you have to reduce the GPMC_CLK by setting GPMCFCLKDIVIDER=1 (ie, divide by 2).
    >GPMC_FCLK = 166MHz GPMC_CLK = 83MHz

    I guess this is example for other Sitara/OMAP device , not for AM335x.
    Because in other device's GPMC_FCLK and GPMC_CLK max frequency are different.
    For example OMAP35x GPMC_FCLK max is 166MHz and GPMC_CLK max are 83MHz.

    Correct. For AM335x, max GPMC_FCLK is 100MHz, see latest TRM section 7.1.2.2 GPMC Clock and Reset Management

    g.f. said:
    So, I guess this Rule1 are only trying to say "PAGEBURSTACCESSTIME must be a multiple of GPMCFCLKDIVIDER+1".

    Yes, see also AM335x TRM, section 7.1.2.3.9.6 GPMC_CLK

    To ensure a correct external clock cycle, the following rules must be applied:
    • (RDCYCLETIME - CLKACTIVATIONTIME) must be a multiple of (GPMCFCLKDIVIDER + 1).
    • The PAGEBURSTACCESSTIME value must be a multiple of (GPMCFCLKDIVIDER + 1).

    g.f. said:
    Q1.Can we cofigure GPMC_CLK to 100MHz whether access modes are Async/Sync/single/burst access?

    Yes, you can. Note that in async mode (NAND mode), GPMC_CLK is not propagated outside the AM335x device.

    g.f. said:
    Q2.We want to know the procedure of how to configure the GPMC_CLK to 100MHz in the Linux SDK.
    Can you please give us an advice?

    What default value you have there? Make sure you have GPMC_CONFIG1[1:0] GPMCFCLKDIVIDER = 0


    Regards,
    Pavel

     



     

  • 0 in reply to Pavel Botev
    Guru 15520 points
    Hi Pavel,

    Thank you for the reply.

    I guess GPMC_CONFIG[1:0] GPMCFCLKDIVIDER are set to GPMCFCLKDIVIDER=1 as default in Linux SDK.
    We understood that we need to set GPMCFCLKDIVIDER to '0' to make GPMC_CLK to be 100MHz
    Where should we modify in the source code of Linux SDK to make GPMC_CLK to be 100MHz?

    best regards,
    g.f.
  • 0 in reply to g.f.
    TI__Guru**** 170625 points

    g.f. said:
    I guess GPMC_CONFIG[1:0] GPMCFCLKDIVIDER are set to GPMCFCLKDIVIDER=1 as default in Linux SDK.

    You can check this, no need to guess. You can use devmem2 tool to read the GPMC_CONFIG1_0 register (physical address 0x50000060). I assume you are using CS0.

    g.f. said:
    We understood that we need to set GPMCFCLKDIVIDER to '0' to make GPMC_CLK to be 100MHz
    Where should we modify in the source code of Linux SDK to make GPMC_CLK to be 100MHz?

    The GPMC_CS_CONFIG1 (GPMC_CONFIG1_0) register is configured in GPMC linux driver

    linux-kernel/drivers/memory/omap-gpmc.c

    Regards,
    Pavel

  • 0 in reply to Pavel Botev
    Guru 15520 points
    Hi Pavel,

    Thank you for supporting us.
    We will try the configuration with AM335x GP EVM.

    best regards,
    g.f.
  • 0 in reply to Pavel Botev
    Guru 15520 points
    Hi Pavel,

    We are trying to configure GPMC_CLK to 100MHz in Linux SDK.
    But we can't find which part of code in linux-kernel/drivers/memory/omap-gpmc.c should be modified.
    Can you please tell us where to change specifically?

    best regards,
    g.f.
  • 0 in reply to g.f.
    TI__Guru**** 170625 points
    g.f.

    Could you please first let me know the value you have in GPMC_CONFIG1_0 register (physical address 0x50000060)? Check this value from user space with devmem2 tool.

    Regards,
    Pavel