TMS320C6678: TSIP Data Rate Options vs TDMU 6 TX and 6 RX channels

Hi,

I've notified the C667x team. Their feedback will be posted here.

Best Regards,
Yordan

Hi,

We had some code for different TSIP link/rate configurations, let me find it out.

Regards, Eric

Hi,

The TSIP driver test example is under pdk_c667x_2_0_x\packages\ti\drv\tsip\example, there are two examples:

• TSIP_evmc6678_c66exampleProject
• TSIP_evmc6678_c66testProject

Those are simple test examples. We had some enhancement work based on the second project, using BIOS-MCSDK 2.1.2.6. I attached the modified file for your reference, it should be compatible with Processor SDK RTOS. Please see the test.h first. enhanced test files.zip

Regards, Eric

Hi Eric,
Thank you for your kind sending the example code.
Will study it and keep you informed.

Best regards,
Hitoshi

Hi Eric,
I read the sample codes, however, I still do not understand about 6 TX and 6 RX channels of TDMU.
There are #define NUM_USED_TSIP_LANES 8 /*Must be 2,4, or 8*/ which means 8 lanes utilized and each has 128 timeslot.
It seems only 1 bitmap is sufficient to handle 8 lanes.

According to the UG, there are 6 bitmaps from 0 to 5 ane each as A and B.
Why 6 TX and 6 RX channels are prepared is that a user can select 12 kinds of bitmaps ( 6 channel x 2 ( A and B)) ?

Could you please let me know exact reason and how to use 6 channels of TDMU?

Thank you very much for your time to answer.
Best regards,
Hitoshi Sugawara