DM648 VPort Capture issue

I'm using customed DM648 board to capture YUV data at 80MHz pixel clock via VPort0. The image size is 2448 x 2048. The YUV data is a striple-tes-data with fixed width 306. But the image I captured via VP0 is like below:

:

image1: the input YUV data is 2448x2048, the capture params setting is 2448x2048.

 The first column and the last two columns data of captured yuv data are wrong.  

I tried to captured YUV data(2448x2048)  via different image width settings in VPORTCAP_Params , and find that when the image width setting is below 2048, the captured YUV data is right.  IfVPORTCAP_Params.fldXStop1 is setted above 2048, the captured YUV data will be wrong. I don't konw why.

.

 image2: the input YUV data is 2448x2048, the capture params setting is 2048x2048. The  

  The captured yuv data is correct

.

   image3: the input YUV data is 2448x2048, the capture params setting is 2080x2048. The  

 The last columns data of captured yuv data is wrong.  The Y data, U data and V data of the last column are all zeros. the yuv2rgb   formula is 

 R = Y + 1.402*(V-128);
G = Y - 0.344*(U-128) -0.714*(V-128);
B = Y + 1.772*(U-128);
 YUV(0,0,0) is RGB(179, 135, 226)， so the last little column zero data is displayed in purple color.

Throught image1~3, u'll find that tha image width > 2048, the captured data is zero.

My  CAP_PARAMS is like below: 

#define CAP_YUV_LINE_SZ (2048)
#define CAP_YUV_NUM_LINES (2048)

#define CAP_PARAMS_CHAN_YUV{ \
VPORT_MODE_YCBCR_8BIT, /* cmode:3 */ \
VPORT_FLDOP_PROGRESSIVE, /* fldOp: FRAME, CF2, CF1. VPORT_FLDOP_PROGRESSIVE: only capture field 1.*/ \
\
VPORT_SCALING_DISABLE, /* scale:1 */ \
VPORT_RESMPL_DISABLE, /* resmpl:1 */ \
VPORTCAP_BPK_10BIT_ZERO_EXTENDED, /* bpk10Bit:2 */ \
\
VPORTCAP_HRST_START_HSYNC, /* hCtRst:1 */ \
VPORTCAP_VRST_START_VSYNC, /* vCtRst:1 */ \
\
VPORTCAP_FLDD_ENABLE, /* fldDect:1 */ \
VPORTCAP_EXC_ENABLE, /* fldInv:1 */ \
VPORTCAP_FINV_DISABLE, /* fldInv:1 */ \
\
0, /* fldXStrt1 */ \
1, /* fldYStrt1 */ \
0, /* fldXStrt2 */ \
1, /* fldYStrt2 */ \
\
(CAP_YUV_LINE_SZ - 1), /* fldXStop1 */ \
(CAP_YUV_NUM_LINES), /* fldYStop1 */ \
(CAP_YUV_LINE_SZ - 1), /* fldXStop2 */ \
(CAP_YUV_NUM_LINES), /* fldYStop2 */ \
\
(CAP_YUV_LINE_SZ >> 3), /* thrld */ \
\
3, /* numFrmBufs */ \
128, /* alignment */ \
VPORT_FLDS_SEPARATED, /* mergeFlds */ \
\
NULL, /* segId */ \
TRUE, /* autoSyncEnable */ \
NULL /* hEdma */ \
}

and the segment program is like below:

tskImg()
{
   capChInfo.chanHandle = FVID_create(vPortCapStrings, IOM_INPUT, &status, (Ptr)&vCapParamsChan, NULL);
   if (IOM_COMPLETED == status)
   {
       status |= FVID_control(capChInfo.chanHandle, VPORT_CMD_START, NULL);
       if (IOM_COMPLETED == status)
       status = FVID_alloc(capChInfo.chanHandle, &(capChInfo.frame));
   }
   while(1)
   {
        send_YUV_data_via_NET();
        BCACHE_inv((Uint8 *)capChInfo.frame->frame.iFrm.y1, (imgSz), TRUE);
        BCACHE_inv((Uint8 *)capChInfo.frame->frame.iFrm.cb1, (imgSz/2), TRUE);
        BCACHE_inv((Uint8 *)capChInfo.frame->frame.iFrm.cr1, (imgSz/2), TRUE);
        status = FVID_exchange(capChInfo.chanHandle, &(capChInfo.frame));
        if (IOM_COMPLETED != status)
                break; 

    }
}

My Question is:

1. Does VPort ensure data integrity  at 80M pixel clock?

2. the VPort FIFO size is 2560 bytes in Y/C capture mode.  and Y buffer is 1280 bytes.  As far as image width 2448 is concerned, how should VPort FIFO threshold  set? 

3. when I captured data with image width 2448,  the vport capture driver will run into _covrRecover() all the time.

   It must be that some error happened. what kind of error will result in this error?  I just change the captured image width below 2048, the demo and driver run well. Why?

 4.  why the captured data will be wrong in width above 2048? what's possible reasons? 

Any help will be appreciated.

dp

dpinglee@163.com