AM5728: PCIe eye diagram improvement

Hello,

We have been looking at the 5G Eye diagram for our custom board using the AM5728 to an Altera FPGA.  We have tried to modify the Link Control and Status 2 register settings for SEL_DEEMP and TX_MARGIN, but neither seem to affect the eye diagram.  While the picture doesn't look bad, we are wondering if there is any settings we could use to maybe improve it. 

Thanks.