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66AK2E05: X66AK2E05

Jared Eberhard
Prodigy 120 points
Part Number: 66AK2E05

I am working on some several proto-type boards that have the X66AK2E05 versions placed on the circuit cards.

I am having issues with the PSC, specifically the turning on/off the Network Coprocessor modules (NETCP) and its associated Clock Domains (PA, SA and SGMIIs). We were able to demonstrate that our VIP code works on a K2E evaluation board just fine (able to toggle the power on/off in terms of the NETCP domain and its Clock Domains) so we believe the VIP code to be working. Other PSC domains are working correctly (PCIe, MSMC, DDR3 EMIF, ARM CorePac, etc.) with their associated Clock Domains.

I was wondering if the PSC for the NETCP domain in the 'X' version (Engineering version of the part) had problems, wasn't instantiated, or is not supported in that specific package.

If it is supported, is there anything different about the PSC from the 'X' version to the normal 66AK2E version?

Thanks,

Jared

  • 0
    TI__Guru**** 161600 points
    Hi Jared,

    I've notified the design team. Their feedback will be posted here.

    Best Regards,
    Yordan
  • 0 in reply to Yordan Kovachev
    TI__Guru* 95265 points
    Hi,

    Please clarify whether power on or power off those domains have problems, or both cases. What is the problem? Did the code stuck on power state transition?

    Where did you get the sequence to power on/off PA, SA, SGMII? I saw in the GEL file ccsv6\ccs_base\emulation\boards\evmk2e\gel:

    Set_PSC_State(PD2, LPSC_PA, PSC_ENABLE);
    Set_PSC_State(PD2, LPSC_SGMII, PSC_ENABLE);
    Set_PSC_State(PD2, LPSC_SA, PSC_ENABLE);

    When power them off, the order would be reversed: SA first, then SGMII, PA.

    I am not sure if the "X" engineering version has any difference to the normal one, I want to confirm your code sequence looks OK and that the same code worked on regular TI K2E EVM first, and why you use "X" version chip for development?

    Regards, Eric
  • 0 in reply to lding
    Prodigy 80 points
    The problem is that the NETCP power and clock domains are off and cannot be turned on. We followed you suggested turn on sequence and all steps failed to change the domain status to ON. We have verified that the power pins to the NETCP section are connected and at the proper voltage. We also confirmed the NETCP PLL is operating at the correct frequency.

    Note that on a K2E EVM the NETCP power and clock domains are on at power up and can be controlled by the same software routines. We also noted that we can access control register spaces for devices that are not powered on: there is no exception and we get all zeros. With power on we get expected register values. Examples are the control registers for the PCIe links. However, for the NETCP, any access to a NETCP, PA , SA control register space results in an exception, AS IF THE HW WAS NOT THERE.
    That is why we question the capabilities of the X version parts we have.

    Do you have any further suggestions to make? Are there any documents specifically for wiring the NETCP section of the chip, including power connections?

    Thank you!

    Regards, Mitch
  • 0 in reply to Mitchell Stanek
    TI__Guru* 95265 points
    Hi,

    Can you clarify: with TI K2E EVM, you can properly turn ON NETCP, PA, SA? Then turn them OFF? Then turn them ON .... if yes, what is the sequence/psudeo code for this?

    Regards, Eric
  • 0 in reply to lding
    Prodigy 80 points
    We can turn off the power and clock domains on the K2E EVM and turn them on again using the sequence you suggested *AND* by using a version that powers on/off the power domain and all clocks as a single command. There does not seem to be dpendency on clock domain order.

    Regards, Mitch
  • 0 in reply to Mitchell Stanek
    TI__Guru* 95265 points
    Hi,

    Thanks for confirmation! So the question is why the same sequence or single command doesn't work on engineering version "X" 66AK2E05. I think they may be prototype chips or not fully tested. I don't know exactly the difference with the production version. Why you use "X" version chip on your boards?

    Regards, Eric
  • 0 in reply to lding
    Prodigy 80 points
    We have the X version because that was the only available part when we placed our order.

    Regarding the PSC tests, I have discovered part of an undocumented state machine during my testing. I tried turning off the NETCP power domain and the 3 associated clock modules, following the reverse of the sequence you gave us in an earlier message. The 3 clock modules did turn off but the power domain did not. I could not find a way to turn off the power domain.

    I then tried to enable the clocks individually, in your suggested sequence, and that worked. There was another state of the clocks that changed when they were turned off by the PSC: the clocks stopped running as shown in the module status registers. This is expected, but when I tried to turn the clocks back on in your sequence, they all failed. This indicates that the clocks must be running before a change in the PSC o/off state can be made. Do you know if some other related state machine transitions control whether or not a power domain can be turned on or off?

    Thanks!

    Regards, Mitch
  • 0 in reply to Mitchell Stanek
    TI__Guru* 95265 points
    Hi,

    I asked our HW team the difference between X66AK2E05 version chip vs production 66AK2E05 version, they will post the answer here.

    Regards, Eric
  • 0 in reply to lding
    Prodigy 120 points

    We have since been able to get Code Composer working on our proto-type boards and are able to run some GEL scripts to get some outputs.

    Right now we are looking into the powering the NETCP power domain (PDSTAT2) and its associated clock domains (MDSTAT7, MDSTAT8, MDSTAT9). We are able to turn on the PDSTAT2 domain but are having some issues with the MDSTATx domains. Below are our PLL settings for the CLKs on the board (we are using the CORECLK input for the NETCP rather than an external clock). All input clocks are 100MHz.

    @                                            pll               pll_m   pll_d  pll_od

    @                                          ----------        ------     ------   -----

    @ #define CORE_PLL     { CORE_PLL,      20,        1,       2 }

    @ #define NETCP_PLL   { NETCP_PLL,    21,        1,       1 }

    @ #define DDR3_PLL     { DDR3A_PLL,   20,        1,       6 }

     

    Below are the GEL script Outputs, it looks like the MDSTAT7/9 are in a 'reserved' state of '14'. Do you know what this means?

     

    Upon power up, PDSTAT2 is not powered on:

    arm_A15_0: GEL Output: ******************** Clock Domain Status (MDSTATn)
    arm_A15_0: GEL Output:     MDSTAT0:    MCKOUT 1  MRSTDONE 1  MRST 1  LRSTDONE 1  LRST 1  STATE 3    (ADDR 0x02350800 RAW 0x00001F03)
    arm_A15_0: GEL Output:     MDSTAT2:    MCKOUT 0  MRSTDONE 1  MRST 0  LRSTDONE 1  LRST 0  STATE 0    (ADDR 0x02350808 RAW 0x00000A00)
    arm_A15_0: GEL Output:     MDSTAT5:    MCKOUT 1  MRSTDONE 1  MRST 1  LRSTDONE 1  LRST 1  STATE 3    (ADDR 0x02350814 RAW 0x00031F03)
    arm_A15_0: GEL Output:     MDSTAT6:    MCKOUT 1  MRSTDONE 1  MRST 1  LRSTDONE 1  LRST 1  STATE 3    (ADDR 0x02350818 RAW 0x00001F03)
    arm_A15_0: GEL Output:     MDSTAT7:    MCKOUT 0  MRSTDONE 1  MRST 0  LRSTDONE 1  LRST 0  STATE 0    (ADDR 0x0235081C RAW 0x00000A00)
    arm_A15_0: GEL Output:     MDSTAT8:    MCKOUT 0  MRSTDONE 1  MRST 0  LRSTDONE 1  LRST 0  STATE 0    (ADDR 0x02350820 RAW 0x00000A00)
    arm_A15_0: GEL Output:     MDSTAT9:    MCKOUT 0  MRSTDONE 1  MRST 0  LRSTDONE 1  LRST 0  STATE 0    (ADDR 0x02350824 RAW 0x00000A00)
    arm_A15_0: GEL Output:     MDSTAT10:    MCKOUT 0  MRSTDONE 1  MRST 0  LRSTDONE 1  LRST 0  STATE 0    (ADDR 0x02350828 RAW 0x00000A00)
    arm_A15_0: GEL Output:     MDSTAT11:    MCKOUT 0  MRSTDONE 1  MRST 0  LRSTDONE 1  LRST 0  STATE 0    (ADDR 0x0235082C RAW 0x00000A00)
    arm_A15_0: GEL Output:     MDSTAT12:    MCKOUT 0  MRSTDONE 1  MRST 0  LRSTDONE 1  LRST 0  STATE 0    (ADDR 0x02350830 RAW 0x00000A00)
    arm_A15_0: GEL Output:     MDSTAT13:    MCKOUT 1  MRSTDONE 1  MRST 1  LRSTDONE 1  LRST 1  STATE 3    (ADDR 0x02350834 RAW 0x00001F03)
    arm_A15_0: GEL Output:     MDSTAT14:    MCKOUT 1  MRSTDONE 1  MRST 1  LRSTDONE 1  LRST 1  STATE 3    (ADDR 0x02350838 RAW 0x00001F03)
    arm_A15_0: GEL Output:     MDSTAT15:    MCKOUT 1  MRSTDONE 1  MRST 1  LRSTDONE 1  LRST 1  STATE 3    (ADDR 0x0235083C RAW 0x00001F03)
    arm_A15_0: GEL Output:     MDSTAT16:    MCKOUT 0  MRSTDONE 1  MRST 0  LRSTDONE 1  LRST 0  STATE 0    (ADDR 0x02350840 RAW 0x00000A00)
    arm_A15_0: GEL Output:     MDSTAT17:    MCKOUT 0  MRSTDONE 1  MRST 0  LRSTDONE 1  LRST 0  STATE 0    (ADDR 0x02350844 RAW 0x00000A00)
    arm_A15_0: GEL Output:     MDSTAT18:    MCKOUT 0  MRSTDONE 1  MRST 0  LRSTDONE 1  LRST 0  STATE 0    (ADDR 0x02350848 RAW 0x00000A00)
    arm_A15_0: GEL Output:     MDSTAT19:    MCKOUT 0  MRSTDONE 1  MRST 0  LRSTDONE 1  LRST 0  STATE 0    (ADDR 0x0235084C RAW 0x00000A00)
    arm_A15_0: GEL Output:     MDSTAT20:    MCKOUT 0  MRSTDONE 1  MRST 0  LRSTDONE 1  LRST 0  STATE 0    (ADDR 0x02350850 RAW 0x00000A00)
    arm_A15_0: GEL Output:     MDSTAT21:    MCKOUT 0  MRSTDONE 1  MRST 0  LRSTDONE 1  LRST 0  STATE 0    (ADDR 0x02350854 RAW 0x00000A00)
    arm_A15_0: GEL Output:     MDSTAT22:    MCKOUT 0  MRSTDONE 1  MRST 0  LRSTDONE 1  LRST 0  STATE 0    (ADDR 0x02350858 RAW 0x00000A00)
    arm_A15_0: GEL Output:     MDSTAT23:    MCKOUT 1  MRSTDONE 1  MRST 1  LRSTDONE 1  LRST 1  STATE 3    (ADDR 0x0235085C RAW 0x00001F03)
    arm_A15_0: GEL Output:     MDSTAT24:    MCKOUT 0  MRSTDONE 1  MRST 0  LRSTDONE 1  LRST 0  STATE 0    (ADDR 0x02350860 RAW 0x00000A00)
    arm_A15_0: GEL Output:     MDSTAT51:    MCKOUT 0  MRSTDONE 1  MRST 0  LRSTDONE 1  LRST 0  STATE 0    (ADDR 0x023508CC RAW 0x00000A00)
    arm_A15_0: GEL Output:     MDSTAT52:    MCKOUT 1  MRSTDONE 1  MRST 1  LRSTDONE 1  LRST 1  STATE 3    (ADDR 0x023508D0 RAW 0x00001F03)
    arm_A15_0: GEL Output: ******************** Power Domain Status (PDSTATn)
    arm_A15_0: GEL Output:     PDSTAT0:    STATE ON (ADDR 0x02350200 RAW 0x00000301)
    arm_A15_0: GEL Output:     PDSTAT1:    STATE ON (ADDR 0x02350204 RAW 0x00000301)
    arm_A15_0: GEL Output:     PDSTAT2:    STATE OFF (ADDR 0x02350208 RAW 0x00000200)
    arm_A15_0: GEL Output:     PDSTAT3:    STATE OFF (ADDR 0x0235020C RAW 0x00000200)
    arm_A15_0: GEL Output:     PDSTAT4:    STATE OFF (ADDR 0x02350210 RAW 0x00000200)
    arm_A15_0: GEL Output:     PDSTAT5:    STATE OFF (ADDR 0x02350214 RAW 0x00000200)
    arm_A15_0: GEL Output:     PDSTAT7:    STATE ON (ADDR 0x0235021C RAW 0x00000301)
    arm_A15_0: GEL Output:     PDSTAT8:    STATE ON (ADDR 0x02350220 RAW 0x00000301)
    arm_A15_0: GEL Output:     PDSTAT9:    STATE OFF (ADDR 0x02350224 RAW 0x00000200)
    arm_A15_0: GEL Output:     PDSTAT10:    STATE OFF (ADDR 0x02350228 RAW 0x00000200)
    arm_A15_0: GEL Output:     PDSTAT11:    STATE OFF (ADDR 0x0235022C RAW 0x00000200)
    arm_A15_0: GEL Output:     PDSTAT12:    STATE OFF (ADDR 0x02350230 RAW 0x00000200)
    arm_A15_0: GEL Output:     PDSTAT13:    STATE OFF (ADDR 0x02350234 RAW 0x00000200)
    arm_A15_0: GEL Output:     PDSTAT14:    STATE OFF (ADDR 0x02350238 RAW 0x00000200)
    arm_A15_0: GEL Output:     PDSTAT15:    STATE OFF (ADDR 0x0235023C RAW 0x00000200)
    arm_A15_0: GEL Output:     PDSTAT16:    STATE ON (ADDR 0x02350240 RAW 0x00000301)
    arm_A15_0: GEL Output:     PDSTAT30:    STATE OFF (ADDR 0x02350278 RAW 0x00000200)
    arm_A15_0: GEL Output:     PDSTAT31:    STATE ON (ADDR 0x0235027C RAW 0x00000301)
    arm_A15_0: GEL Output: *************************** End of Power Domain Snapshot

    arm_A15_0: GEL Output: ******************** Activate All Power Domains (PDCTNn)

    arm_A15_0: GEL Output:     Setting PDCTL0    ON!
    arm_A15_0: GEL Output:     Setting PDCTL1    ON!
    arm_A15_0: GEL Output:     Setting PDCTL2    ON!
    arm_A15_0: GEL Output:     Setting PDCTL3    ON!
    arm_A15_0: GEL Output:     Setting PDCTL4    ON!
    arm_A15_0: GEL Output:     Setting PDCTL5    ON!
    arm_A15_0: GEL Output:     Setting PDCTL7    ON!
    arm_A15_0: GEL Output:     Setting PDCTL8    ON!
    arm_A15_0: GEL Output:     Setting PDCTL9    ON!
    arm_A15_0: GEL Output:     Setting PDCTL10    ON!
    arm_A15_0: GEL Output:     Setting PDCTL11    ON!
    arm_A15_0: GEL Output:     Setting PDCTL12    ON!
    arm_A15_0: GEL Output:     Setting PDCTL13    ON!
    arm_A15_0: GEL Output:     Setting PDCTL14    ON!
    arm_A15_0: GEL Output:     Setting PDCTL15    ON!
    arm_A15_0: GEL Output:     Setting PDCTL16    ON!
    arm_A15_0: GEL Output:     Setting PDCTL30    ON!
    arm_A15_0: GEL Output:     Setting PDCTL31    ON!
    arm_A15_0: GEL Output:     Complete!
    arm_A15_0: GEL Output: ***************************
    arm_A15_0: GEL Output: *************************** Power Domain Snapshot
    arm_A15_0: GEL Output: ***************************

    arm_A15_0: GEL Output: ******************** Clock Domain Status (MDSTATn)
    arm_A15_0: GEL Output:     MDSTAT0:    MCKOUT 1  MRSTDONE 1  MRST 1  LRSTDONE 1  LRST 1  STATE 3    (ADDR 0x02350800 RAW 0x00001F03)
    arm_A15_0: GEL Output:     MDSTAT2:    MCKOUT 0  MRSTDONE 1  MRST 0  LRSTDONE 1  LRST 0  STATE 0    (ADDR 0x02350808 RAW 0x00000A00)
    arm_A15_0: GEL Output:     MDSTAT5:    MCKOUT 1  MRSTDONE 1  MRST 1  LRSTDONE 1  LRST 1  STATE 3    (ADDR 0x02350814 RAW 0x00031F03)
    arm_A15_0: GEL Output:     MDSTAT6:    MCKOUT 1  MRSTDONE 1  MRST 1  LRSTDONE 1  LRST 1  STATE 3    (ADDR 0x02350818 RAW 0x00001F03)
    arm_A15_0: GEL Output:     MDSTAT7:    MCKOUT 0  MRSTDONE 1  MRST 0  LRSTDONE 1  LRST 0  STATE 14    (ADDR 0x0235081C RAW 0x00000A0E)
    arm_A15_0: GEL Output:     MDSTAT8:    MCKOUT 0  MRSTDONE 1  MRST 0  LRSTDONE 1  LRST 0  STATE 0    (ADDR 0x02350820 RAW 0x00000A00)
    arm_A15_0: GEL Output:     MDSTAT9:    MCKOUT 0  MRSTDONE 1  MRST 0  LRSTDONE 1  LRST 0  STATE 14    (ADDR 0x02350824 RAW 0x00000A0E)
    arm_A15_0: GEL Output:     MDSTAT10:    MCKOUT 0  MRSTDONE 1  MRST 0  LRSTDONE 1  LRST 0  STATE 0    (ADDR 0x02350828 RAW 0x00000A00)
    arm_A15_0: GEL Output:     MDSTAT11:    MCKOUT 0  MRSTDONE 1  MRST 0  LRSTDONE 1  LRST 0  STATE 0    (ADDR 0x0235082C RAW 0x00000A00)
    arm_A15_0: GEL Output:     MDSTAT12:    MCKOUT 0  MRSTDONE 1  MRST 0  LRSTDONE 1  LRST 0  STATE 0    (ADDR 0x02350830 RAW 0x00000A00)
    arm_A15_0: GEL Output:     MDSTAT13:    MCKOUT 1  MRSTDONE 1  MRST 1  LRSTDONE 1  LRST 1  STATE 3    (ADDR 0x02350834 RAW 0x00001F03)
    arm_A15_0: GEL Output:     MDSTAT14:    MCKOUT 1  MRSTDONE 1  MRST 1  LRSTDONE 1  LRST 1  STATE 3    (ADDR 0x02350838 RAW 0x00001F03)
    arm_A15_0: GEL Output:     MDSTAT15:    MCKOUT 1  MRSTDONE 1  MRST 1  LRSTDONE 1  LRST 1  STATE 3    (ADDR 0x0235083C RAW 0x00001F03)
    arm_A15_0: GEL Output:     MDSTAT16:    MCKOUT 0  MRSTDONE 1  MRST 0  LRSTDONE 1  LRST 0  STATE 0    (ADDR 0x02350840 RAW 0x00000A00)
    arm_A15_0: GEL Output:     MDSTAT17:    MCKOUT 0  MRSTDONE 1  MRST 0  LRSTDONE 1  LRST 0  STATE 0    (ADDR 0x02350844 RAW 0x00000A00)
    arm_A15_0: GEL Output:     MDSTAT18:    MCKOUT 0  MRSTDONE 1  MRST 0  LRSTDONE 1  LRST 0  STATE 0    (ADDR 0x02350848 RAW 0x00000A00)
    arm_A15_0: GEL Output:     MDSTAT19:    MCKOUT 0  MRSTDONE 1  MRST 0  LRSTDONE 1  LRST 0  STATE 0    (ADDR 0x0235084C RAW 0x00000A00)
    arm_A15_0: GEL Output:     MDSTAT20:    MCKOUT 0  MRSTDONE 1  MRST 0  LRSTDONE 1  LRST 0  STATE 0    (ADDR 0x02350850 RAW 0x00000A00)
    arm_A15_0: GEL Output:     MDSTAT21:    MCKOUT 0  MRSTDONE 1  MRST 0  LRSTDONE 1  LRST 0  STATE 0    (ADDR 0x02350854 RAW 0x00000A00)
    arm_A15_0: GEL Output:     MDSTAT22:    MCKOUT 0  MRSTDONE 1  MRST 0  LRSTDONE 1  LRST 0  STATE 0    (ADDR 0x02350858 RAW 0x00000A00)
    arm_A15_0: GEL Output:     MDSTAT23:    MCKOUT 1  MRSTDONE 1  MRST 1  LRSTDONE 1  LRST 1  STATE 3    (ADDR 0x0235085C RAW 0x00001F03)
    arm_A15_0: GEL Output:     MDSTAT24:    MCKOUT 0  MRSTDONE 1  MRST 0  LRSTDONE 1  LRST 0  STATE 0    (ADDR 0x02350860 RAW 0x00000A00)
    arm_A15_0: GEL Output:     MDSTAT51:    MCKOUT 0  MRSTDONE 1  MRST 0  LRSTDONE 1  LRST 0  STATE 0    (ADDR 0x023508CC RAW 0x00000A00)
    arm_A15_0: GEL Output:     MDSTAT52:    MCKOUT 1  MRSTDONE 1  MRST 1  LRSTDONE 1  LRST 1  STATE 3    (ADDR 0x023508D0 RAW 0x00001F03)
    arm_A15_0: GEL Output: ******************** Power Domain Status (PDSTATn)
    arm_A15_0: GEL Output:     PDSTAT0:    STATE ON (ADDR 0x02350200 RAW 0x00000301)
    arm_A15_0: GEL Output:     PDSTAT1:    STATE ON (ADDR 0x02350204 RAW 0x00000301)
    arm_A15_0: GEL Output:     PDSTAT2:    STATE ON (ADDR 0x02350208 RAW 0x00000301)
    arm_A15_0: GEL Output:     PDSTAT3:    STATE ON (ADDR 0x0235020C RAW 0x00000301)
    arm_A15_0: GEL Output:     PDSTAT4:    STATE OFF (ADDR 0x02350210 RAW 0x00000200)
    arm_A15_0: GEL Output:     PDSTAT5:    STATE ON (ADDR 0x02350214 RAW 0x00000301)
    arm_A15_0: GEL Output:     PDSTAT7:    STATE ON (ADDR 0x0235021C RAW 0x00000301)
    arm_A15_0: GEL Output:     PDSTAT8:    STATE ON (ADDR 0x02350220 RAW 0x00000301)
    arm_A15_0: GEL Output:     PDSTAT9:    STATE OFF (ADDR 0x02350224 RAW 0x00000200)
    arm_A15_0: GEL Output:     PDSTAT10:    STATE OFF (ADDR 0x02350228 RAW 0x00000200)
    arm_A15_0: GEL Output:     PDSTAT11:    STATE OFF (ADDR 0x0235022C RAW 0x00000200)
    arm_A15_0: GEL Output:     PDSTAT12:    STATE OFF (ADDR 0x02350230 RAW 0x00000200)
    arm_A15_0: GEL Output:     PDSTAT13:    STATE OFF (ADDR 0x02350234 RAW 0x00000200)
    arm_A15_0: GEL Output:     PDSTAT14:    STATE OFF (ADDR 0x02350238 RAW 0x00000200)
    arm_A15_0: GEL Output:     PDSTAT15:    STATE OFF (ADDR 0x0235023C RAW 0x00000200)
    arm_A15_0: GEL Output:     PDSTAT16:    STATE ON (ADDR 0x02350240 RAW 0x00000301)
    arm_A15_0: GEL Output:     PDSTAT30:    STATE OFF (ADDR 0x02350278 RAW 0x00000200)
    arm_A15_0: GEL Output:     PDSTAT31:    STATE ON (ADDR 0x0235027C RAW 0x00000301)
    arm_A15_0: GEL Output: *************************** End of Power Domain Snapshot

    arm_A15_0: GEL Output: ******************** PASS_PLL (same as the NETCP)

    arm_A15_0: GEL Output:  PASS_PLL_CTL0 register:   0x09000500 (0x02620358)
    arm_A15_0: GEL Output:  PLLD[5:0]:    0
    arm_A15_0: GEL Output:  PLLM[18:6]:   20
    arm_A15_0: GEL Output:  BYPASS[23]:   0
    arm_A15_0: GEL Output:  BWADJ[31:24]: 9
    arm_A15_0: GEL Output:  PASS_PLL_CTL1 register:   0x00002040
    arm_A15_0: GEL Output:  PLLRESET[14]: Reset ** DEASSERTED ** to PLL
    arm_A15_0: GEL Output:  BWADJ[11:8]:  0
    arm_A15_0: GEL Output:  BWADJ[11:0] (combined):    9

    If there are other GEL scripts that set up/read the Ethernet initialization or run other related tests that can help us understand why we are not powering on the clocks successful please let us know.

    Thanks,

    Jared

     

  • 0 in reply to Jared Eberhard
    TI__Guru* 95265 points

    Jared,

    I looked at your NETCP PLLM/PPLD/CLKOD configuration.

    For our K2E EVM, the input reference clock is 100MHz, by looking at the GEL file under CCS: ccsv6\ccs_base\emulation\boards\evmk2e\gel, the

    if ((papllctl0val_final != 0x09080500) || (papllctl1val_final != 0x00002040))
     {
      return 1;
     }

    so the 0x262_0358 = 0x09080500, this is PLLD= 0, PLLM = 20, CLKOD = 1. By math, 100MHz*(PLLM+1)/(PLLD+1)/(CLKOD+1) = 1050MHz. Then from K2E datasheet Figure 10-27 NETCP PLL Block Diagram, this 1050MHz is divided by 3 =350MHz into NETCP. 350MHz is the maximum clock speed you can use.

    In your configuration, PASS_PLL_CTL0 register:   0x09000500 (0x02620358) =====> The CLKOD = 0. So the input to NETCP is too high. Can you double check?

    Regards, Eric