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RTOS: GPIO latency

Vinay Kumar Shettar
Intellectual 410 points

Other Parts Discussed in Thread: SYSBIOS

Tool/software: TI-RTOS

I am using AM572x EVM board and Running TI RTOS in Cortex M4.

When I am running a program and configured GPIO as OUTPUT and doing GPIO HIGH and then to GPIO LOW and measuring the time using logic analyzer.

1.    When using GPIO_write() API, it takes 48us to do GPIO HIGH and then to GPIO LOW.
2.    When I use GPIOPinWrite() CSL API then it takes 6us to do GPIO HIGH and then to GPIO LOW.
3.    When I use GPIOMultiplePinsWrite CSL API then it takes 3us which does both GPIO HIGH and then to GPIO LOW.

It  looks like Cortex M4 is running at much slower clock speed than it supposed to run which is 212.8MHz.

When I check th config file Platform Information it shows the following:
Device name DRA7XX Clock rate(MHz) 212.8
Platform name ti.platforms.evmAM572x

Please let me know what is causing GPIO operation taking this much of time.
If it is set to lower clock speed, please let me know how to set the clock speed to Max.  

  • 0
    TI__Guru**** 393215 points
    The RTOS team have been notified. They will respond here.
  • 0
    TI__Guru** 116840 points
    Vinay,

    The typical latency for M4 in RTOS environment is documented in bios_6_xx_x_xx\packages\ti\sysbios\benchmarks\doc-files. However, I suspect, the performance on AM57x device will be slightly lower due to the complexity of the interconnect, Unicache/MMU and the pin multtiplexing etc.

    We recently did some benchmarking on M4 with the GPIO LLD for our evaluation. We used the GPIO LED blink example on IDK(industrial) EVM to measure the M4 cycle required to toggle a GPIO4 pin. The time taken to write to GPIO was 305 cycles with Unicache and MMU enabled. Here are our findings:
    • With No unicache MMU (AMMU)settings: 6900 cycles.
    • With TI AMMU setting and GPIO CSL call to toggle pin : 305 cycles.

    GPIO4 is on the L4 hierarchy along with other peripherals like the SPI peripheral so I would expect similar performance with SPI but for other peripherals you might be able improve performance by using EDMA engine to service the peripheral. Can you please share some use case details and performance expectation so that we can provide appropriate guidance on this issue.

    Regards,

    Rahul


    Note: All the performance discussed in this post was done at M4 @213 Mhz
  • 0 in reply to Rahul Prabhu
    Intellectual 410 points

    Thank you Rahul.  Following is the use case and performance expectation.

    We have connected the external MicroController via SPI with DataR interrupt Gpio Pin. The MicroController interrupt is the most critical interrupt in the system. We need to react on that interrupt and start reading out data on the SPI line in less than 10µs. Otherwise the MicroController's internal FIFO gets overwritten and the system cannot recover from that any more. Therefore we have to verify the hard real time capabilities of the Cortex-M4 with RTOS with respect to GPIO and SPI.

  • 0 in reply to Vinay Kumar Shettar
    Intellectual 410 points
    Hi,
    Could you please guide us on the above use case and performance expectation.

    Regards,
    Vinay.