We are currently doing for the SC3 workaround for memory protection to meet AUTOSAR OS standard with TI TDA3x processor and we are trying to use the firewall features in the Interconnect module and we have a couple of questions for clarification. We have two questions at the end of this description. (more detail is in the attached document)
1. Feasibility study: Autosar Memory protection for TDA3x
2. Objective/Requirement: To implement memory protection feature on TDA3x as
proposed by Autosar
3. Problem Statement:
A range based memory protection(Dividing the physical memory into sections and and
assigning the attributes(READ, WRITE, EXECUTE etc) to the individual sections) is to be
implemented.
A dedicated ARM core Memory Protection Unit (MPU) provided this feature where in the
sections can be defined and attributes can be assigned to individual memory sections.But, the
ARM Cortex M4 core for TDA3x does not include the Memory Protection Unit (MPU).
So an alternate way has to be found out and implemented which will confirm to the
Autosar Memory protection feature.
4. Assessment of options: Using Interconnect module.
The Interconnect module within the TDA3X provided Firewall feature.
Firewall: A programmable feature integrated in a target agent or L4 interconnect to
prevent unauthorized access to or from a module. A firewall can be configured using three
criteria:
– Initiator requesting access
– Address space access
– Type of access
5. Implementation Summary:
We have implemented L3 firewall based memory protection with IPU as Initiator agent and
EMIF (which is part of L3 main)as target agent and with some initial level of testing we can say
that Autosar Memory Protection feature can be implemented using Firewall.
6. Concerns & Questions:
1) Our Observation was that when IPU Cache is enabled the Firewall protection fails as some
of instructions and data are already cached.
Is it possible that L3 firewall can be made to work with Cache enabled ?
The IPU cache is part of L1 and L2 level memory so is L3 firewall handling sufficient ?
2) We have implemented the memory protection using L3 level firewall and thus memory
protection for EMIF, OCMC and GPMC etc can be supported. But, the IPU’s Internal memory
is not part of L3 level memory hence if IPU’s Internal memory is used then memory protection
is not possible with current implementation.
How can we implement memory protection for L1 and L2 level of memory ?
The Memory protection should be region based memory protection(We should be able
to define start and end address along with access attributes for a region)
