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Jacinto 6 platform: latest schematics reference for suspend-to-RAM (ideally for J6RSP)

Stefan_Haas
Mastermind 25262 points

Hello,

can you point me to the latest schematics reference for suspend-to-RAM (ideally for J6RSP)?

Thanks, Stefan

  • 0
    TI__Mastermind 42515 points
    Hi Stefan,

    I have forwarded your question to an expert.

    Regards,
    Yordan
  • 0 in reply to Yordan Kamenov
    TI__Guru 52335 points
    The J6Entry EVM does include the hardware configuration/options to support the different levels of suspend-2-ram.

    Level 1: DDR memory content preserved across a warm reset.
    - From hardware perspective, this mode requires a pull-down on CKE

    Level 2: DDR memory content preserved across a cold reset.
    - From hardware perspective, this mode requires Level 1 (PD on CKE) plus it requires external control of DDR Reset

    Level 3: DDR memory content preserved across a power cycle
    - From hardware perspective, this mode requires Level 1 and Level 2 (PD on CKE, external DDR Reset control) and separate power control for DDR/VREF

    There are silicon errata which might affect recovering from self refresh mode, and I currently in discussions to determine if/how they affect these different levels. I will update the thread when I have more clear understanding.

    Thanks.
    Robert
  • 0 in reply to Robert Eschler
    TI__Mastermind 42515 points
    Hi,

    There was a suggested answer and since there has been no activity on this thread for more than a week,
    the suggested answer was marked as verify. Please feel free to select the "Reject Answer" button and reply with more details.

    Regards,
    Yordan
  • 0 in reply to Yordan Kamenov
    TI__Guru 52335 points
    Yes - I did confirm the silicon errata is specific to warm reset conditions only, and does not affect cold/power on reset conditions - and therefore does not impact suspend to ram operation.
    Thanks
    Robert
  • 0 in reply to Robert Eschler
    TI__Mastermind 25262 points

    Hello,

    can you please add which J6RSP rails are kept active (if at all) for suspend to RAM? and if there is any rail, what is the current consumption?

    Thanks, Stefan

  • 0 in reply to Stefan_Haas
    TI__Guru 52335 points

    It depends on which level of Suspend To RAM you are referring.  For levels I and II - all power rails remain active.  For Level 3, only DDR power rails remain active (No SoC power rails are powered).  In all 3 levels - the DDR memory device is place into self refresh mode.  The memory data sheet should specify the power requirements for self refresh mode.