Hi,
I'm trying to understand how data moves from a 64-pin DSP DDR data bus to 4, 16-bits DDR SDRAMs.
According to the DDR3 Memory Controller datasheet, "the default burst size is 8, the DDR3 memory controller returns 8 words of data for every read command. Word size is nothing but the DDR3 interface bus width."
This makes sense since the DSP ddr data pins [15:0] interfacing with a [15:0] SDRAM will require a total of 8 burst to achieve a single read/write into the SDRAM core (8n prefetch architecture). Or in other words as the datasheet explains, the DDR3 memory controller returns 8 words of data for every read command..
However, the 64 DSP DDR data pins are split into four ranges [15:0], [31:16], 47:32], [63:48] to each [15:0] SDRAM (total of 4 SDRAMs).
1) So, when a read command occurs, and say for example, I'd like to read a Uint64, then the SDRAMs return 8 words of data per [15:0], [31:16], [47:32], [63:48]? This is assuming that the Uint64 data is stored and split in 16-bits into each of the 4 SDRAM. So, we would be getting extra data, but those data extra would be masked.
I couldn't find much information about this. I'm using the CC6678 DSP
I look forward to your response,
Best
Alvaro
