AM5728: Field detection logic for interlaced video

Prasad said:

On AM5728 video input port, how is the field ID detected in case of discrete sync capture?

Please check TRM document section 9.4.5.6.9 Field ID Determination Using Dedicated Signal.

Prasad said:

Is it safe to rely on the  VPDMA write descriptor for detecting the field ID?

Yes. The VIP_PARSER extracts the FIELD ID information from the sync (VS/HS or VS/FID) and sets the FID bit on the frame it sends to VPDMA.

The VPDMA simply saves the FID bit value and includes it in the write descriptor.

From TRM, below description on DISCRETE_BASIC_MODE field of VIP_PORT_A register. FID determined by VSYNC skew only in Normal Discrete Mode. 

This register is valid for Discrete Sync mode only. 0 = RW 0x0
Normal Discrete Mode. Hsync Style Capture operates as
follows: - Captures line starting from HSYNC inactive to
active condition. - VSYNC determined by sync window. -
FID can be determined by VSYNC skew or captured from
pin at first pixel in first line. ACTVID style capture works
as follows: - Captures line during contiguous ACTVID
envelope. - VSYNC is captured at the first pixel in each
line. - FID is captured on first pixel of ACTVID window. 1
= Basic Discrete Mode. When using hsync with Hsync
Style Capture operates as follows: - The last line of active
video ends on the pixel clock cycle where VSYNC
transitions from inactive to active. - FID pin value is
captured on this cycle and is used for the next field. - FID
detection by VSYNC skew is not allowed. ACTVID style
capture works as follows: - VSYNC is expected to
transition from inactive to active between ACTVID
window. - This VSYNC transition allows the next line in an
ACTVID envelope to be sent to a new VPDMA buffer. -
FID value is determined by the FID pin value on the cycle
where VSYNC transitions from inactive to active. In basic
discrete mode, there is no Vertical Ancillary Data.
Therefore, VPDMA descriptors should not use Ancillary
Data channels.