OMAP3530: is the GPMC same as AM3715/03?

Jose said:

The question is if I can connect a NOR flash in the same way to the OMAP.

I see no reason that you could not use the same implementation on the OMAP3, the GPMC peripherals work in the same way.

I am curious why you would want to use NOR like this in place of NAND which has the same basic interface functionality at a lower cost? I am guessing this is a reliability concern?

Thanks for the answers.

You're right Bernie, it is a reliability issue.

Jose

Hi,

I have given the schematic a thought, and it looks like the circuit is wrong !

It needs an inverter on the latch gate:

the SN74LVC16373A is transparent when LE is high.

From the Figure 6-12 of the OMAP3530 datasheet (Async write, muxed ad/dat), the ALE goes high during the write cycle which would loose the latched state and copy the data on the address lines!

I couldn't find any latched with active-low gates, and I am concerned about the timing if I add an inverter...

Philippe,

I think you're right!  I've seen similar things done before, but this one is just a little different.  I think a workable solution would be to use SN74ALVCH16374 and tie nadv_ale to the CLK pin.

I'm separately contacting the author of that wiki page to see about fixing it.

Best regards,
Brad

Hi Brad,

thanks for your answer.

I think that using an edge triggered flip flop won't work either.

In the OMAP datasheet, figure 6-5 (synchronous burst read) the timing from when the address is valid to the first rising edge of ALE is not specified. I believe that the address will be properly captured by the external flip flops on the second edge.

This will violate the setup time of my memory (Axcell P30): the address is captured by the memory when ADV is rising the second time, and it must be stable 10ns before this edge.

I am wondering how the customer designs you mentioned above worked out!

(unless they don't use burst mode...)

Here's the description of the ADV# pin from the data sheet you referenced:

"During synchronous read operations, addresses are latched on the rising edge of ADV#,
or on the next valid CLK edge with ADV# low, whichever occurs first."

That said, it doesn't sound like you need an external latch at all.  Can't you connect the data pins to the corresponding address pins directly?  In other words, it sounds like the latch capability is built into your NOR flash.

To your other point I believe some of the other customers were using the async mode.

Brad

Hi Brad,

I agree with you for the synchronous reads. However, the datasheet is not clear about the behavior of ADV# pin in asynchronous write mode:

In the pin description, it says "In asynchronous mode, ADV# can be either driven high to latch the address or held low throught the read cycle."

In the 5.4 (Write) section, no mention of ADV is made, it is written "the address is latched on the rising edge of WE or CE". And in the AC characteristics, no mention of the ADV setup/hold time is made in the write section.

I am very puzzled by this memory, because I don't see why the latch would be "bypassed" only in write modes. (moreover the memory will latch the address at the beginning of the cycle, because it doesn't know if the transaction will be a read or a write). Things are unclear, I've tried to reach Numonyx support but they are less reactive than you are in this summer holydays time...

I am afraid of not putting a latch on my board, if finally it doesn't work I will have to throw my boards away...

If you have seen a working design with the P30 family and without external latch, I would be very interested to head about it !

I don't think the latch is bypassed for write mode, but I agree the documentation isn't great!

Table 26: AC Write Specifications has a couple of specs related to ADV# and Note 12 beneath the table says, "These specs are required only when ADV# is used to latch address."  I see those timings (W21 and W22) in Figure 27 "Synchronous Read-to-Write Timing (Easy BGA)".  Comparing back to the OMAP specs it looks like we easily meet those requirements.

Philippe,

Any other thoughts?  Did you finish your schematic?  When do you get boards?

Best regards,
Brad

Hi Brad,

I haven't concluded on this topic yet. I have the same opinion as you (no latch should be necessary), but I'd like to hear from Numonyx support and have a definitive answer.I e-mailed them a few weeks ago, they didn't answer and I have no other means to reach them.

I am putting ~20K€ at risk on PCB and board production...

I have to make a final decision at the end of the month for P&R, and I will get the boards early november.

Regards

Philippe

Philippe,

Any other updates on this issue?  I was about to make some edits to that original wiki article with the incorrect info but thought I'd see if you had any other thoughts or suggestions.

Best regards,
Brad

Philippe,

FYI, I just made a few edits to that wiki page.  I appreciate your spotting the original errors and I hope my edits address the issue for you and others.  Let me know if you have further feedback.  Also, I'd be very grateful if you could keep us in the loop as you get boards, etc.  From our discussions here on the forum I am fairly confident that your straight hookup to the P30 would be successful, but of course getting confirmation on real hardware is always much better.

Best regards,
Brad

Hi Brad,

I will try to post some news when I get the boards. (expected in October)

Don't hesitate to contact me if I forget about this.

Regards

Philippe

Philippe MAIRE said:

Hi Brad,

I will try to post some news when I get the boards. (expected in October)

Don't hesitate to contact me if I forget about this.

Regards

Philippe

 

hi,

any news?

Jose

Hello Jose,

Yes, this is ok to do with the OMAP35x devices.  The GPMC is the same for both AM37 and OMAP35, the AM37 just supports 100MHz insted of just 83MHz like the OMAP35x.

Hi

Due to the space taken by an external latch, we decided to use NAND flash.

Philippe