I'm looking at the SPRUFM9F USB2.0 manual, trying to figure out how EP 0 sends the last or only) data packet in response to a setup packet that has a Read Standard Device Request.
Figure 5 on page 25 seems to imply one loads the FIFO, sets TxPktRdy, and sets DataEnd; and section 2.7.1.1.3 also says “When the last data packet has been written to the FIFO, the PERI_CSR0 register should be written to set the TXPKTRDY bit and to set the DATAEND bit (bit 3) (indicating that there is no more data after this packet).”
However, section 2.7.1.1.5 says
“If the endpoint 0 is in TX state, the interrupt indicates that the core has received an IN token and data
from the FIFO has been sent. The software must respond to this either by placing more data in the FIFO if
the host is still expecting more data or by setting the DATAEND bit to indicate that the data phase is
complete.”
So, do I wait for the interrupt to write DATAEND (per 2.7.1.1.5); or should I set it directly after setting the TXPKTRDY bit (per 2.7.1.1.3), before the IN token packet has arrived?
Thanks!
JJ
