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C6745 Audio Configuration Issues

Other Parts Discussed in Thread: TLV320AIC3007, TLV320AIC3106

Hi,

We used the C6747 starter kits, CCS v3.3, BIOS 5.33.05, PSP 1.30.01 and we were able to have our application playing audio wave files successfully.  We moved to our actual hardware and having issues with the audio.  My questions are:

1. The starter kits uses 24.576MHz external clock for MCLK.  Our hardware use DSP AHCLKX1 for MCLK.  We configured the registers as below.  AHCLKX1 signal does not available all the time.  What could be the the cause?

Mcasp_HwSetupData mcaspRcvSetup =

{

    /* .rmask    = */ 0xFFFFFFFF, /* All the data bits are to be used     */

    /* .rfmt     = */ 0x000080F0, /*

                                   * 0 bit delay from framsync

                                   * MSB first

                                   * No extra bit padding

                                   * Padding bit (ignore)

                                   * slot Size is 32

                                   * Reads from DMA port

                                   * NO rotation

                                   */

    /* .afsrctl  = */ 0x00000000, /* burst mode,

                                   * Frame sync is one bit

                                   * Rising edge is start of frame

                                   * externally generated frame sync

                                   */

    /* .rtdm     = */ 0x00000001, /* slot 1 is active (DSP)               */

    /* .rintctl  = */ 0x00000003, /* sync error and overrun error         */

    /* .rstat    = */ 0x000001FF, /* reset any existing status bits       */

    /* .revtctl  = */ 0x00000000, /* DMA request is enabled or disabled   */

    {

#ifdef EVM_FLAG

         /* .aclkrctl  = */ 0x00000000,

         /* .ahclkrctl = */ 0x00000000,

#else

         /* .aclkrctl  = */ 0x00000023,

         /* .ahclkrctl = */ 0x00008046,

#endif

         /* .rclkchk   = */ 0x00000000

    }

};

Mcasp_HwSetupData mcaspXmtSetup =

{

    /* .xmask    = */ 0xFFFFFFFF, /* All the data bits are to be used     */

    /* .xfmt     = */ 0x000080F0, /*

                                   * 0 bit delay from framsync

                                   * MSB first

                                   * No extra bit padding

                                   * Padding bit (ignore)

                                   * slot Size is 32

                                   * Reads from DMA port

                                   * NO rotation

                                   */

    /* .afsxctl  = */ 0x00000000, /* burst mode,

                                   * Frame sync is one bit

                                   * Rising edge is start of frame

                                   * externally generated frame sync

                                   */

    /* .xtdm     = */ 0x00000001, /* slot 1 is active (DSP)               */

    /* .xintctl  = */ 0x00000007, /* sync error,overrun error,clK error   */

    /* .xstat    = */ 0x000001FF, /* reset any existing status bits       */

    /* .xevtctl  = */ 0x00000000, /* DMA request is enabled or disabled   */

    {

#ifdef EVM_FLAG

         /* .aclkxctl  = */ 0x00000000,

         /* .ahclkxctl = */ 0x00000000,

#else

         /* .aclkxctl  = */ 0x00000023,

         /* .ahclkxctl = */ 0x00008046,

#endif

         /* .xclkchk   = */ 0x00000000

    },

};

static void AUDD_GblCallback( int32_t arg_ );

// McBsp channel parameters

Mcasp_ChanParams  mcasp_chanparam[Audio_NUM_CHANS]=

{

    {

        0x0001,                    // number of serialisers

        {Mcasp_SerializerNum_0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 },

        &mcaspRcvSetup,

        TRUE,

        Mcasp_OpMode_TDM,          // Mode (TDM/DIT)

        Mcasp_WordLength_32,

        NULL,

        0,

        NULL,

        AUDD_GblCallback,

        1,                        // number of TDM channels

        Mcasp_BufferFormat_1SER_1SLOT,

        TRUE,

        TRUE

    },

    {

        0x0001,                   // number of serialisers

        {Mcasp_SerializerNum_5,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 },

        &mcaspXmtSetup,

        TRUE,

        Mcasp_OpMode_TDM,

        Mcasp_WordLength_32,      // word width

        NULL,

        0,

        NULL,

        AUDD_GblCallback,

        1,                        // number of TDM channels

        Mcasp_BufferFormat_1SER_1SLOT,

        TRUE,

        TRUE

    }

};

Audio_ChannelConfig audioChanParamsIN =

{

    // channel 0 (RX)

    (Ptr)&mcasp_chanparam[0],

    {   // codec [0]

        {

             11025/*RESP_SAMPLING_RATE*/,  // sampling rate for codec

               70,  // gain (%) for codec

             0x00,

             0x00

        }

    }

};

 

Audio_ChannelConfig audioChanParamsOUT =

{

    //  channel 1 (TX)

    (Ptr)&mcasp_chanparam[1],

    {

        // codec [1]

        {

            11025/*AUDIO_SAMPLING_RATE*/,  // sampling rate

               70,   // gain (%) for codec

             0x00,

             0x00

        }

    }

};

2. When AHCLKX1 signal available, our application got locked up in SIO_issue().  Please comment.

3. Our board has TLV320AIC3007 and the EVM has TLV320AIC3106.  From the data sheet comparison, these 2 codecs provides the same functionalities to play audio wave files and sampling audio inputs.  Any difference that we should pay attention on the TLV320AIC3007.

4. Please point us to the information of configuring the codec speaker amp.

Thanks

  • Dennis Nguyen said:

    1. The starter kits uses 24.576MHz external clock for MCLK.  Our hardware use DSP AHCLKX1 for MCLK.  We configured the registers as below.  AHCLKX1 signal does not available all the time.  What could be the the cause?

     

    It looks like your code is configuring McASP for burst mode.  The userguide states that in burst mode "Additional clocks after the slot and before the next frame sync edge are ignored."  So it's possible that the clock is only active during a valid data slot.

     

    Dennis Nguyen said:

     

    2. When AHCLKX1 signal available, our application got locked up in SIO_issue().  Please comment.

    Your application is probably waiting for McASP during an active data slot.

     

    Dennis Nguyen said:

     

    3. Our board has TLV320AIC3007 and the EVM has TLV320AIC3106.  From the data sheet comparison, these 2 codecs provides the same functionalities to play audio wave files and sampling audio inputs.  Any difference that we should pay attention on the TLV320AIC3007.

    4. Please point us to the information of configuring the codec speaker amp.

     

    I'm not very familiar with the codec chips.  You may want to consult with the Audio Converters forum: http://e2e.ti.com/support/data_converters/audio_converters/default.aspx

     

  • Hi,

    I have a few queries regarding your configuration.

    1. Is the I2C slave address for the codec same on your custom hardware?

    2. Can you please eloborate on your clock configuration ( who is supplying the bit clock and the frame sync)

    regards,

    imtiaz

  • Hi imtiaz,

    Imtiaz SMA said:
    Is the I2C slave address for the codec same on your custom hardware?

    Yes, I just checked that. Im using a AIC3007. Code is from the AIC31 support. (ie AIC3106). I2C address is 0x18 for both.

    I debugged it last night and it looks like the stoppage is when the Codec doesn’t respond to the I2C reads.

    I will chek to see if the Codec is in Reset.

    Imtiaz SMA said:
    Can you please eloborate on your clock configuration ( who is supplying the bit clock and the frame sync)

    Clocks (MCLK, BCLK, and WCLK from McAsp lines

    MCLK = AHCLKX1  (24 Mhz)

    BCLK = ACLKX1

    WCLK = AFSX1

    EVM is the same, except they have a MCLK crystal clock of 24.576 Mhz

    Thanks,

    Dennis