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AM5726: OCMC shared memory

David Beaulieu
Expert 1280 points
Part Number: AM5726


Hi, 

I have a few question about the OCMC shared memory connected to the L3 interconnect in the Sitara processor. 

  1. What is the latency of these memory region compared to the DSP L2 SRAM and DDR3? Is the access speed closer to the L2 RAM or closer to the DDR3?
  2. Are these memory region cacheable when being accessed in the DSP and the M4?

Thanks,

- David

  • 0
    TI__Guru**** 393215 points
    Hi,

    1. Please see Figure 14-1 from the AM572x TRM Rev. H. The ARM MPU has direct access to DDR, while the other cores access it over L3. All cores access OCMC RAM over L3. So the answer to this is different, depending on which core accesses the OCMC RAM.
    2. I will ask the AM57x team to comment.
  • 0
    TI__Guru**** 161600 points
    Hi David,

    The DSP can cache an external memory, see the TMS320C66x DSP Cache User Guide (www.ti.com/.../sprugy8.pdf), Section 2.3 Cacheability:
    "For L1D and L2, you can control whether external memory addresses are cacheable or noncacheable. Each external memory address space of 16M bytes is controlled by a memory attribute register (MAR) bit (0 = noncacheable, 1 = cacheable). The memory attribute registers are documented in TMS320C66x CorePac User Guide in ‘‘Related Documentation from Texas Instruments’’ on page ø-x. For instance, to enable caching
    for the external memory range from 8000 0000h to 80FF FFFFh, the CSL function CACHE_enableCaching(CACHE_MAR128) can be used."

    The IPU Cortex M4 uses the IPUx_UNICACHE & IPUx_UNICACHE_MMU submodules, see Section 7.3.3 IPUx_UNICACHE & Section 7.3.4 IPUx_UNICACHE_MMU in the AM57xx TRM.

    Best Regards,
    Yordan
  • 0 in reply to Biser Gatchev-XID
    Expert 1280 points

    Hi, 

    I my case, the DSP and the M4 would be accessing the OCMC RAM.

    Regards,

    - David

  • 0 in reply to Yordan Kovachev
    Expert 1280 points
    Hi ,

    To enable caching in the DSP, do I use the virtual address or the physical address?
    In my case, the CMEM region physical address is 0xA0000000 and is mapped to 0x8C000000. To enable cache, should I use 0x8c000000 or 0xA0000000?

    Regards,
    - David
  • 0 in reply to David Beaulieu
    TI__Guru**** 161600 points
    Hi David,

    What software is this? Linux kernel works with virtual addresses, so you may need to remap the physcal address space before using it.

    For bare metal application (no OS) I think you'll be fine working with the physical addresses. I am NOT aware of how things should be done in RTOS.

    Best Regards,
    Yordan
  • 0 in reply to Yordan Kovachev
    Expert 1280 points

    Hi Yordan,

    I am running Linux on the ARM and RTOS on the DSP and M4. I already have a CMEM region for shared memory between the ARM, DSP and M4 working in OCMC.

    Regards,

    - David