AM5728: MMC1_CLK INPUTENABLE bit

matusan

Guru 10235 points

Part Number: AM5728

Hello, TI Experts,

We have a question about "INPUTENABLE-bit" of mmc1_clk on AM5728.

We found the "note" as below from TRM(SPRUHZ6H) "Table 25-3. Description of eMMC/SD/SDIOi host controller I/O’s"

- For mmc2_clk, mmc3_clk and mmc4_clk signals to work properly, the INPUTENABLE bit of

the appropriate CTRL_CORE_PAD_x registers must be set to 0x1 by software.

So we understand "INPUTENABLE" should be set 0x1 for mmc2_clk, mmc3_clk and mmc4_clk.

Question:

Why doesn't include "mmc1_clk" in the "note"?

We also find the comment "Only MMC1 and MMC2 have loopback circuit" from TRM(SPRUHZ6H)

"Figure 25-2. eMMC/SD/SDIOi Controller Connected to an eMMC, SD, or SDIO Card"

We are confused from followings;

-MMC1: loopback-yes, note for INPUTENABLE-no -> Why?

-MMC2: loopback-yes, note for INPUTENABLE-yes

-MMC3: loopback-no, note for INPUTENABLE-yes -> Why?

-MMC4: loopback-no, note for INPUTENABLE-yes -> Why?

We would appreciate if you tell us the recommended setting for "INPUTENABLE" of mmc1_clk

With explanation of mmc_clk loopback mechanism .

Best regards

over 9 years ago

0 Biser Gatchev-XID over 9 years ago

TI__Guru**** 393215 points

Hi,

This is probably a typo in the TRM. I have asked the AM57x team to check. They will respond here.

0 matusan over 9 years ago in reply to Biser Gatchev-XID

Guru 10235 points

Hi,

Thank you very much for your kindness.
I really appreciate your help.

I am waiting for their reply.

Best regards,

0 Yordan Kovachev over 9 years ago

TI__Guru**** 161600 points

Hi Matusan,

MMC2, MMC3 & MMC4 need the INPUTENABLE bit set, because of a clock re-synchronization to guarantee the timings described in DM.

MMC1 has a different implementation of the I/O cell and that is why the loopback mechanism is enough to meet the CLK timings & there is no need to set the INPUTENABLE bit.

Hope this helps.

Best Regards,
Yordan

0 matusan over 9 years ago in reply to Yordan Kovachev

Guru 10235 points

Hi,

Thank you for your prompt replay.　

We really appreciate your help.

Our under standing is as follows;

- MMC2, MMC3 & MMC4 need the INPUTENABLE bit set,

because clock re-synchronization requires input-buffer.

- MMC1 don't need to set the INPUTENABLE bit,

because the loopback mechanism don't require input-buffer.

Based on this understanding,

How do we understand "CORE_CONTROL_SPARE_RW_MMC2_LOOPBACK-bit"

from TRM(SPRUHZ6H) "Table 18-1151. CTRL_CORE_CONTROL_SPARE_RW"?

We would appreciate if you tell us the recommended way to use "CORE_CONTROL_SPARE_RW_MMC2_LOOPBACK-bit".

- Can we activate the same loopback mechanism of MMC1?

(Then MMC2 don't need to set the INPUTENABLE bit.)

Best regards

0 matusan over 9 years ago in reply to matusan

Guru 10235 points

Hello Yordan,

Do you have any update?

Our customer is waiting for the answer.
So I'd like to answer to the customer as below.
- MMC2, MMC3 & MMC4 need the INPUTENABLE bit set,
because clock re-synchronization requires input-buffer.
- MMC1 don't need to set the INPUTENABLE bit,
because the loopback mechanism don't require input-buffer.
- If "CORE_CONTROL_SPARE_RW_MMC2_LOOPBACK-bit" is set to 0x0,
Loopback clock from the I/O pad is selected.
In this case, MMC2 don't need to set the INPUTENABLE bit,
because the loopback mechanism don't require input-buffer.
Please see TRM(SPRUHZ6H) "Table 18-1151. CTRL_CORE_CONTROL_SPARE_RW"

If you have some comment/recommendation, please tell us.

Best regards,

0 Yordan Kovachev over 9 years ago in reply to matusan

TI__Guru**** 161600 points

Hi,

- If "CORE_CONTROL_SPARE_RW_MMC2_LOOPBACK-bit" is set to 0x0,
Loopback clock from the I/O pad is selected.
In this case, MMC2 don't need to set the INPUTENABLE bit,
because the loopback mechanism don't require input-buffer

This is not true. Follow the note after Table 25-3. Description of eMMC/SD/SDIOi host controller I/O’s:

NOTE: For mmc2_clk, mmc3_clk and mmc4_clk signals to work properly, the INPUTENABLE bit of the appropriate CTRL_CORE_PAD_x registers must be set to 0x1 by software. This is because the eMMC/SD/SDIO controller uses the input from the pad as loopback clock, which the controller can use for read capture depending on the mode it is in.

Best Regards,
Yordan

0 matusan over 9 years ago in reply to Yordan Kovachev

Guru 10235 points

Hello Yordan,

Thank you for your prompt replay.　

We really appreciate your help.

Our understanding from your explanation is as follows;

-If CORE_CONTROL_SPARE_RW_MMC1_LOOPBACK-bit is set to 0x0

(Loopback clock from the I/O pad is selected ), MMC1 don't need to set the INPUTENABLE bit.

-If CORE_CONTROL_SPARE_RW_MMC2_LOOPBACK-bit is set to 0x0

(Loopback clock from the I/O pad is selected ), MMC2 need the INPUTENABLE bit set.

Is this understanding correct?

Based on TRM(SPRUHZ6H) "Figure 25-2. eMMC/SD/SDIOi Controller Connected to an eMMC, SD, or SDIO Card", the loopback-mechanism of MMC2 seems to be that of MMC1.

We would appreciate if you tell us why the setting value of INPUTENABLE is different from MMC1 and MMC2.

Best regards,

0 Yordan Kovachev over 9 years ago in reply to matusan

TI__Guru**** 161600 points

Hi,

Sorry for the delayed response.

Is this understanding correct?

Yes, this is correct.

We would appreciate if you tell us why the setting value of INPUTENABLE is different from MMC1 and MMC2.

From what I understood, there is a difference in the implementations of the I/O cells of MMC1 & all other MMC interfaces. However I am not aware of the exact differences & I can't disclose such SoC details.

Best Regards,
Yordan

0 matusan over 9 years ago in reply to Yordan Kovachev

Guru 10235 points

Hi, Yordan

Thank you very much for your kindness.
I really appreciate your help.

Best regards,

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AM5728: MMC1_CLK INPUTENABLE bit