Part Number: AM3352
Tool/software: Linux
Are any known issues around timer2 system timer interrupts causing suspend failures in Processor-SDK 1.03?
A customer reporting they sporadically see the “Kernel suspend failure” message during Deepsleep0 (DS0) suspend/resume test cycles.
Further study seems to point to the DMtimer2 interrupts in /arc/arm/mach-omap2/timer.c _suspend() and _resume() functions
Does that make sense?
Please see detailed debug steps below:
I have been able to reproduce an instance of “Kernel suspend failure” on my [hardware] with debug code in place to read the INTC_SIR_IRQ register after the nonzero return from cpu_suspend(). The value is 0x44, which is decimal 68. From this, I look at /proc/interrupts and see that INTC 68 is ‘gp_timer’. This interrupt is set up in …/arch/arm/mach-omap2/timer.c and is the hardware timer2 interrupt, which is the ‘clockevent’ system timer.
the previous debug code read each of the four INTC_PENDING_IRQn registers, but they were all 0. The TRM seems to imply that these will not show masked interrupts. That’s why I switched to reading INTC_SIR_IRQ.
Timer.c does have _suspend() and _resume() functions. Omap_clkevt_suspend() only performs a module idle operation, and I have verified that AM33XX_CM_PER_TIMER2_CLKCTRL register is 0x00030000, which is the disabled state. But the _suspend does not disable the interrupt.
So I’m asking if there are any known issues around timer2 system timer interrupts causing suspend failures in Processor-SDK 1.03?