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DM365 CPLD GPIO problem

Joe Tanaka
Prodigy 70 points

I am trying to use the GPIO of the CPLD on connector J23.

In output mode, everything works fine: I write 0x00 (output mode) to register 720 and I can toggle the GPIO by writing to register 721.

In input mode, I cannot read the GPIO. I write 0xFF to register 720 (all input). Reading register 721 only gives me the value previsouly written to it and not the status of the inputs.

A quick look at the CPLD code did not reveal any obvious problem. Any idea?

  • 0
    TI__Expert 5955 points

    Hello,

    The addresses of the CPLD registers are non-linear because some of the address lines get pin-muxed away when different peripherals are enabled.  It could be that the address that you are using is not where is actually is.  You can find the addresses in the evmdm365.c of the BSL:

    static Uint8 *cpld_addrmap[CPLD_NUMREGS] =

    {

                    (Uint8 *)0x04000000, // Register 0

                    (Uint8 *)0x04000008, // Register 1

                    (Uint8 *)0x04000010, // Register 2

                    (Uint8 *)0x04000018, // Register 3

                    (Uint8 *)0x04000400, // Register 4

                    (Uint8 *)0x04000408, // Register 5

                    (Uint8 *)0x04000410, // Register 6

                    (Uint8 *)0x04000418, // Register 7

                    (Uint8 *)0x04000800, // Register 8

                    (Uint8 *)0x04000808, // Register 9

                    (Uint8 *)0x04000810, // Register 10

                    (Uint8 *)0x04000818, // Register 11

                    (Uint8 *)0x04000c00, // Register 12

                    (Uint8 *)0x04000c08, // Register 13

                    (Uint8 *)0x04000c10, // Register 14

                    (Uint8 *)0x04000c18, // Register 15

                    (Uint8 *)0x04001000, // Register 16

                    (Uint8 *)0x04001008, // Register 17

                    (Uint8 *)0x04001010, // Register 18

                    (Uint8 *)0x04001018, // Register 19

                    (Uint8 *)0x0400f800, // Register 20

                    (Uint8 *)0x0400f808, // Register 21

                    (Uint8 *)0x0400f810, // Register 22

                    (Uint8 *)0x0400f818, // Register 23

                    (Uint8 *)0x0400fc00, // Register 24

                    (Uint8 *)0x0400fc08  // Register 25

    };

    If the register addresses are correct, you might have to ask Spectrum Digital support for additional help since it is specific to the EVM CPLD.

    Thanks.

    -Tai Nguyen

  • 0 in reply to Tai Nguyen
    Prodigy 70 points

    Thanks for the response. We confirmed that the GPIO reads do no work and reported this to Spectrum Digital. In the mean time we fixed the CPLD because we could not wait.