In the AM335x Technical Reference Manual, it mentions in section 13.3.6.2.1.3 that a FIFO Underflow is possible for the LCD controller. I am wondering what the screen behavior is during this scenario. Here is what my expectation would be... Since the FIFO is read based upon the LCD pixel clock speed, we can't control that and the LCD controller keeps feeding the LCD some value every LCD pixel clock cycle. Once the LCD has completed reading, our DMA might still be placing values in the FIFO. So there are two possibilities, either the LCD controller is smart enough to always clear the FIFO before we start again or there will be stale data in the FIFO the next time the LCD starts reading values.
We have not seen this issue yet and have many test units out there. I am wondering if we should still handle the underflow condition or if we don't see it during our testing how big of a deal it is.
Thanks.
David
