Hi,
I have an issue in which timeslots are shiftted during run-time.
We have several AIC33 codecs on the MCBSP bus, using EDMA3 and DSP is transmitting the frame-sync.
Sample rate = 48Khz.
Buffers are in the internal memory.
We have encountered this issue a long time ago and found errata that defines workarounds with one of them to lower the sample rate. We have updated sampling rate to be 16Khz and problem disappeared.
However, today we require to implement the high frequency.
Previously we tried updating the EDMA priority to be the highest and did not help.
2 questions:
1. I have not managed to find again this errata - maybe someone can send it or give a link to it?
2. Any ways/ideas to solve the issue?
Thanks in davance for the help
Yoav