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TMS320C6424: Timeslot shifting

Part Number: TMS320C6424

Hi,

I have an issue in which timeslots are shiftted during run-time.

We have several AIC33 codecs on the MCBSP bus, using EDMA3 and DSP is transmitting the frame-sync.

Sample rate = 48Khz.

Buffers are in the internal memory.

We have encountered this issue a long time ago and found errata that defines workarounds with one of them to lower the sample rate. We have updated sampling rate to be 16Khz and problem disappeared.

However, today we require to implement the high frequency.

Previously we tried updating the EDMA priority to be the highest and did not help.


2 questions:

1. I have not managed to find again this errata - maybe someone can send it or give a link to it?

2. Any ways/ideas to solve the issue?

Thanks in davance for the help

Yoav

  • Hi Yoav,

    I've forwarded this to the experts. Their feedback should be posted here.

    BR
    Tsvetolin Shulev
  • Yoav

    The errata usage notes 2.1.2 and 2.1.13 are the known issues documented

    If you are already using internal memory and highest priority for EDMA, i am not aware of any other workarounds.

    Please see if  the Q/TC servicing McBSP is exclusively used for McBSP only. It would be good to confirm that you are seeing the issues with stand alone or simultaneous traffic on DDR from other sources? Make sure that the PBBPR register value is set to 0x20 if you have multiple masters accessing DDR (as specified in usage note 2.1.1)

    Hope this helps. 

  • Yoav,

    How is your data configured in the serial stream? Is each datum 8-bits or 16-bits in size? Are you sending pairs of data and splitting them into separate channels later?

    One solution I have worked out with my customers is to configure the McBSP for 32-bit data so the EDMA does not need to access the RDR as often, which tends to avoid data loss.

    Regards,
    RandyP