Hi Tis,
We have the custom board with dm8168 and use the following link to fine tune the DDR related parameters in UBoot code.(http://processors.wiki.ti.com/index.php/DM816x_C6A816x_AM389x_DDR3_Init)
After running the slave ratio search program...I have got the DDR parameter set as below:
#define RD_DQS_GATE_LANE3 ((emif == 0) ? 0x177 : 0x15d) /*BYTE3 OPT values from CCS slave ratio*/
#define RD_DQS_GATE_LANE2 ((emif == 0) ? 0x18c : 0x176) /*BYTE2 OPT values from CCS slave ratio*/
#define RD_DQS_GATE_LANE1 ((emif == 0) ? 0x1be : 0x1af) /*BYTE1 OPT values from CCS slave ratio*/
#define RD_DQS_GATE_LANE0 ((emif == 0) ? 0x1cd : 0x1ca) /*BYTE0 OPT values from CCS slave ratio*/
#define RD_DQS_LANE3 ((emif == 0) ? 0x47 : 0x3f) /*BYTE3 OPT values from CCS slave ratio*/
#define RD_DQS_LANE2 ((emif == 0) ? 0x3c : 0x41) /*BYTE2 OPT values from CCS slave ratio*/
#define RD_DQS_LANE1 ((emif == 0) ? 0x41 : 0x42) /*BYTE1 OPT values from CCS slave ratio*/
#define RD_DQS_LANE0 ((emif == 0) ? 0x35 : 0x3a) /*BYTE0 OPT values from CCS slave ratio*/
#define WR_DQS_LANE3 ((emif == 0) ? 0x6c : 0x67) /*BYTE3 OPT values from CCS slave ratio*/
#define WR_DQS_LANE2 ((emif == 0) ? 0x90 : 0x88) /*BYTE2 OPT values from CCS slave ratio*/
#define WR_DQS_LANE1 ((emif == 0) ? 0xb8 : 0xa7) /*BYTE1 OPT values from CCS slave ratio*/
#define WR_DQS_LANE0 ((emif == 0) ? 0xc0 : 0xc4) /*BYTE0 OPT values from CCS slave ratio*/
with this parameters...I have built the UBoot code and got the u-boot.noxip.bin then flash to nand flash. Unfortunately, I cant see uboot console output after booting from nand flash.
But when I use MLO image built from the same u-boot source code and boot from SD card...It's OK...I could enter the UBOOT prompt. why?
I try another DDR parameters as below and test again..
The MLO image and u-boot.noxip binary both could boot successfully(I could enter UBOOT prompt).
#define RD_DQS_GATE_LANE3 ((emif == 0) ? 0x170 : 0x15e) /*BYTE3 OPT values from CCS slave ratio*/
#define RD_DQS_GATE_LANE2 ((emif == 0) ? 0x187 : 0x16f) /*BYTE2 OPT values from CCS slave ratio*/
#define RD_DQS_GATE_LANE1 ((emif == 0) ? 0x1b8 : 0x1a7) /*BYTE1 OPT values from CCS slave ratio*/
#define RD_DQS_GATE_LANE0 ((emif == 0) ? 0x1c9 : 0x1b9) /*BYTE0 OPT values from CCS slave ratio*/
#define RD_DQS_LANE3 ((emif == 0) ? 0x45 : 0x40) /*BYTE3 OPT values from CCS slave ratio*/
#define RD_DQS_LANE2 ((emif == 0) ? 0x3b : 0x40) /*BYTE2 OPT values from CCS slave ratio*/
#define RD_DQS_LANE1 ((emif == 0) ? 0x42 : 0x42) /*BYTE1 OPT values from CCS slave ratio*/
#define RD_DQS_LANE0 ((emif == 0) ? 0x32 : 0x3a) /*BYTE0 OPT values from CCS slave ratio*/
#define WR_DQS_LANE3 ((emif == 0) ? 0x73 : 0x68) /*BYTE3 OPT values from CCS slave ratio*/
#define WR_DQS_LANE2 ((emif == 0) ? 0x85 : 0x85) /*BYTE2 OPT values from CCS slave ratio*/
#define WR_DQS_LANE1 ((emif == 0) ? 0xb3 : 0xa9) /*BYTE1 OPT values from CCS slave ratio*/
#define WR_DQS_LANE0 ((emif == 0) ? 0xbf : 0xbe) /*BYTE0 OPT values from CCS slave ratio*/
The two DDR parameters almost the same...the parameter is too critical to booting?
Are there something wrong..?
Thanks
BR,
Steven
