AM3352: GPMC_A0 with 16-bit NOR flash

Kummi

Part Number: AM3352
Other Parts Discussed in Thread: TMDSICE3359

Hi,

We need a clarification with regards to connecting 16bit NOR-Flash through GPMC.
As per the TRM "Table 7-5" for a 16 bit device, GPMC_A0 is not used whereas in case
of AM335x ICE EVM(TMDSICE3359) GPMC_A0 seems to the connected to A0 of the memory device.
Is there any reason for this connection? Is this a mistake in the EVM design.

In actual design we don't need to connect GPMC_A0 to Memory's A0 pin instead connect GPMC_A1 to Memory's A0 pin?

Best Regards
Kummi

over 8 years ago

0 Biser Gatchev-XID over 8 years ago

TI__Guru**** 393215 points

In the ICEv2 schematic the signal GPMC_A0 does not come from the processor, but from the U26 latch on the same page. The NOR flash in this schematic is connected in 16-bit mode (BYTE pin tied high), therefore A0 on the NOR is the LSB of a 16-bit address.

0 Kummi over 8 years ago in reply to Biser Gatchev-XID

Mastermind 6220 points

Hi Biser,

Thank you for the quick reply.

Which means the actual GPMC_Ax signals from AM335x is not used in the EVM
but multiplex signals GPMC_ADx are used through U26 latch?

Best Regards
Kummi

0 Biser Gatchev-XID over 8 years ago in reply to Kummi

TI__Guru**** 393215 points

Yes, this is correct.

0 Kummi over 8 years ago in reply to Biser Gatchev-XID

Mastermind 6220 points

Hi Biser,

Will this spec(GPMC_A0) apply for 16bit NOR-Flash in XIP mode?
As per the TRM, "Pin used in XIP_MUX2 mode" has A0(GPMC_A0) also.
If A0 is not not used we have only 2KB left during the initial access?

Could you please let me know if there is a reference schematics on XIP NOR with AM335x.

Best Regards
Kummi

0 Biser Gatchev-XID over 8 years ago in reply to Kummi

TI__Guru**** 393215 points

This means that pin GPMC_A0 will be initialized by the ROM code pinmuxing. It does not mean that address A0 will be issued. Table 7-5 applies for correct addressing. Address LSB will be issued on GPMC_A1.

0 Kummi over 8 years ago in reply to Biser Gatchev-XID

Mastermind 6220 points

Hi Biser,

Thank you.

If A0 is not issued we have only 2KB (A1 to A11), during the initial access?
And the initialization code should be less than 2KB.

Could you please let me if there is any reference schematics on XIP NOR.

Best Regards
Kummi

0 Biser Gatchev-XID over 8 years ago in reply to Kummi

TI__Guru**** 393215 points

You have 2k addresses, but this is a 16-bit device, so you have 4KB of data in this address space.

0 Kummi over 8 years ago in reply to Biser Gatchev-XID

Mastermind 6220 points

Thank you Biser,

With regards to the upper address lines (A12–A27), in case of XIP mode,
the TRM mentions we need to isolate the upper address lines during NOR Boot as below.

"External logic is needed to isolate the upper address lines (A12–A27) of the
NOR flash from the device pins and drive them low during non-muxed NOR boot."

What could be the preferred way to isolate the upper address lines?
Since this application has cost and space constraint, we cannot use additional Logic IC.
Will it be OK to use simple Resistors to Pull down the upper address lines?

Best Regards
Kummi

0 Biser Gatchev-XID over 8 years ago in reply to Kummi

TI__Guru**** 393215 points

Yes, this is possible and has been done by other customers.

0 Kummi over 8 years ago in reply to Biser Gatchev-XID

Mastermind 6220 points

Hi Biser,

I am sorry, I have additional question about NOR Flash connection in XIP Mode.

As per the "Table 26-9. Pins Used for Non-Muxed NOR Boot" the lower address lines A0 to A11,
should be connected as per the table(LCD_DATA0 to LCD_AC_BIAS_EN pin)
but with respect to the remaining upper address lines (A12–A27),
especially above gpmc_a16, is it optional(software controlled) to be connected to
either GPMC_A0(gpmc_a16) or LCD_DATA12(gpmc_a16) whichever is available?

Best Regards
Kummi

0 Biser Gatchev-XID over 8 years ago in reply to Kummi

TI__Guru**** 393215 points

Yes, these pins are not initialized by the ROM code. They should be initialized early in the boot process (first 4KB).

0 Kummi over 8 years ago in reply to Biser Gatchev-XID

Mastermind 6220 points

Hi Biser,

Thank you.
Please let me ask one more clarification.

In XIP Mode(MUX2), with regards to the upper address lines (A12–A27),
we will use external pull down to drive these pins low during non-muxed NOR boot.

But the NOR flash requires address lines A0-A24, so we won't be using A25 to A27.
Do we need to pull down the address lines even though if it is not used.

And looking into to the datasheet BALL RESET STATE of pins A25 to A27 seems to be LOW,
so we think it is not necessary to pull down A25 to A27.
Please let me know if this assumption is correct.

Best Regards
Kummi

0 Biser Gatchev-XID over 8 years ago in reply to Kummi

TI__Guru**** 393215 points

This is correct, but be careful which address lines you connect to the NOR. Refer to Table 7-5 from the TRM.

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AM3352: GPMC_A0 with 16-bit NOR flash