AM5728: GPU power domain doesn't switch to OFF state

Hi,

I would like to know how to way GPU power domain is off.

My customer is trying to change the state from on state to off state of GPU power domain.  But it is not failed.

The below is customer's sequence. Pleasse see it.

GPU power domain ON sequence: (This is successful.)

[1] Write 0x3 to [1:0] POWERSTATE bit in PM_GPU_PWRSTCTRL(0x4AE07200) register.
    (POWERSTATE : ON State)
   
[2] Write 0x3 to [1:0] CLKTRCTRL bit in CM_GPU_CLKSTCTRL(0x4A009200) register.
    (CLKTRCTRL : SW_AUTO)

[3] Clear [1:0] MODULEMODE bit in CM_GPU_GPU_CLKCTRL(0x4A009220) register to ZERO.
    (MODULEMODE : Module is disabled by SW.)

[4] Wait until the value of CM_GPU_GPU_CLKCTRL(0x4A009220) register becomes 0x0007 0000.
    (IDLEST : Module is disabled and cannot be accessed)
    (STBYST : Module is in standby)

[5] Clear [1:0] PM_GPU_PWRSTCTRL bit in CM_GPU_CLKCTRL(0x4AE07200) register to ZERO.
    (POWERSTATE : OFF State)

[6] Wait until the value of PM_GPU_PWRSTST(0x4AE7204) register becomes 0x00\000000.
    (POWERSTATEST : Power domain is OFF)

[7] Write 0x3 to [1:0] POWERSTATE bit in PM_GPU_PWRSTCTRL(0x4AE07200) register.
    (POWERSTATE : ON State)

[8] Write 0x2 to [1:0] CLKTRCTRL bit in CM_GPU_CLKSTCTRL(0x4A009200) register.
    (CLKTRCTRL : SW_WKUP)

[9] Write 0x2 to [1:0] MODULEMODE bit in CM_GPU_GPU_CLKCTRL(0x4A009220) register.
    (MODULEMODE : Module is explicitly enabled.)

[10] Wait until the value of [17:16]IDLEST bit in CM_GPU_GPU_CLKCTRL(0x4A009220) register becomes 0x0.
    (IDLEST : Module is fully functional, including OCP)

[11] Write 0x1 to [5:4]STANDBY_MODE bit and 0x1 to [3:2] IDLE_MODE bit in GPU SYSCONFIG(0x5600FE10) register.
    (STANDMY_MODE : No-standby)
    (IDLE_MODE : No-standby)

When the above sequence is executed, th value of PM_GPU_PWRSTST(0x4AE7204) register becomes 0x00000037.
   (GPU_MEM_STATEST : Memory is ON)
    (LOGICSTATEST : Logic in domain is ON)
    (POWERSTATEST : Power domain is ON-ACTIVE)
This value is the same as customer7s expectation.

GPU power domain OFF sequence: (This is not successful)
[1] Clear GPU SYSCONFIG(0x5600FE10) register to ZERO.

[2] Clear [1:0] POWERSTATE bit in PM_GPU_PWRSTCTRL(0x4AE07200) register  to ZERO.
    (POWERSTATE : OFF State)
[3] Write 0x1 to [4] LOWPOWERSTATECHANGE in PM_GPU_PWRSTCTRL(0x4AE07200)register.
    (LOWPOWERSTATECHANGE : Force change)
[4] Wait until the value of [4]LOWPOWERSTATECHANGE bit in PM_GPU_PWRSTCTRL(0x4AE07200)register becomes 0x0.
    → It has never becomed [4]bit to 0x0(wait time : 1000msec).

[5] Wait until the value of [1:0]POWERSTATEST bit in PM_GPU_PWRSTST(0x4AE07204)register becomes 0x0
    → It has never becomed [1:0]bit to 0x0(wait time : 1000msec)

[6] Write 0x1 to [1:0] CLKTRCTRL bit in CM_GPU_CLKSTCTRL(0x4A009200) register.
    (CLKTRCTRL : SW_SLEEP)

[4] Write 0x2 to [1:0] IDLEST bit in CM_GPU_GPU_CLKCTRL(0x4A009220) register.
    (IDLEST : Module is fully functional, including OCP)

When the above sequence is executed, the value of PM_GPU_PWRSTST(0x4AE07204) register remains 0x00000037.
The customer's expecting value is 0x00000000. The register's value is not changed.

Question:
1) Is the above OFF sequence correct? If something is wrong, please let me know.

2) If OFF sequence is completed, the value of PM_GPU_PWRSTST(0x4AE07204) register becomes to 0x00000000. Is my understanding right?

Please advise me.

I appreciate quick reply.

Best regards,

Michi