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TCI6630K2L: How is the queue map for Keystone II?

Eric Liang
Prodigy 140 points
Part Number: TCI6630K2L

Hi all,

I've read the Multicore Navigator user guide (SPRUGR9H) for the queue map information (Page 119). As for C6630K2L, it does not describe clearly enough.

What is worse, is that when I read the CSL code (v2.1.1.0, got from MCSDK 3.1.4.7) about the queue map definition, i.e. csl_device_interrupt.h, the queue map information is different from the user guide's.

Such as:

EDMA0 queue pend queues (560-569, totally 10 queues)  from user guide       V.S.     QMSS_MAX_EDMA0_QUEUE (6) and QMSS_MAX_UNASSIGNED_SET_0_QUEUE_BASE (4) from CSL.

Most of the conflicts are about CIC.

And there are so many UNASSIGNED queues in CSL definition.

I am confused.

Could you help me to understand the queue map of C6630K2L?

Is there a clear description on this queue map?

Thank you very much!

  • 0
    TI__Guru 65405 points
    Hi Eric,

    I've forwarded this to the experts. Their feedback should be posted here.

    BR
    Tsvetolin Shulev
  • 0
    TI__Mastermind 21025 points

    Perhaps part of your confusion is due to the fact that QMSS queues are not solely dedicated for a single purpose.  In the queue map tables, queues that are not listed are "general purpose" queues that do not have any mapping to special hardware capability.  Other queues, such as queue pend queues and Tx DMA queues have a wire that connects the queue's state to an interrupt or a specific Tx pktDMA channel.  If you aren't using that functionality the queue may be used as a simple queue pend queue.

    I am not aware of any errors in either the Navigator user guide or the CSL.  If you make use of the QMSS LLD in the MCSDK, you can let it choose queues for you, based on a particular "queue type".  This may help alleviate your confusion.  See "Qmss_QueueType" in ti/drv/qmss.