Hello,
I've recently started working with the new csl_6472. My main use so far is the EMAC (csl_emac).
Before, I worked with the CSL for C6486, which worked just fine.
The new CSL seems more supportive of multicore, in the sense that every core has its own initializations (before, the master core initialized all the data for all the cores).
My problem is, that it seems the new CSL assumes all the cores use the same emac device, that is, the same variable, in the exact same memory. My cores each run a different program, and are unaware of one another, and (ideally) do not have any common memory.
The way I see it, I have two choices:
1. Define some common memory, and put the emac device variable there. This is problematic for me because a. Like I said, I'd rather the cores know little about one another and b. Wouldn't the variable, being global, be initialized whenever a new core is run? That way, running a new core would destroy all my settings and the work of all other cores...
2. "Fooling" the emac device into thinking it has been initialized, and working with the given CSL. This sounded like the better idea for me, but I don't seem to be able to make it work, that is, I can initialize the EMAC and use send_packet without any errors, but only the master core actually sends the packets.
Any ideas for a better way to do this? Is the CSL going to stay this way?
Is there any multicore EMAC example?
Thanks in advance.
