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AM3354: Padconf registers and LCDC questions

g.f.
Guru 15520 points
Part Number: AM3354


Hi,

I have questions about AM3354 Control Module register for each pins and LCD Controller.

*****************************
About Control Module Register
*****************************
Q1. In AM335x TRM(spruh73o) page.1468 9.3.1.50 conf_<module>_<pin> Register,
    it said "reset value of conf_<module>_<pin> register bit[6] is pad-dependent".
    Where should I check the reset value of each pins?
    Should I see BUFFER STRENGTH which are written in AM335x datasheet Table 4-1. Pin Attributes?
    If yes, if the pin's buffer strenght is 6mA, will above bit[6] be set to slower slew rate in default?

Q2. In AM335x TRM(spruh73o) page.1468 9.3.1.50 conf_<module>_<pin> Register,
    it said "reset value of conf_<module>_<pin> register bit[4] and bit[3] are pad-dependent".
    If the pins are in Hi-Z after reset release, what is the default value for above bit[4] and bit[3]?

*****************************
About LCD Controller
*****************************
Q3. In AM335x TRM page.1945 13.5.1.26 CLKC_ENABLE Register,
    there are no value written for each clock enalbe bit.
    What value should I set to enable these clocks? Is it "1"?

Q4.If we don't use DMA engine of LCD Controller,
   can I set the dma_clk_en bit of CLKC_ENABLE register to 0(disable) ?

Q5.If we don't use DMA engine of LCD Controller,
   can I leave the following register to default value?
   -LCDDMA_CTRL
   -LCDDMA_FB0_BASE
   -LCDDMA_FB0_CEILING
   -LCDDMA_FB1_BASE
   -LCDDMA_FB1_CEILING

Q5.If we don't use DMA engine of LCD Controller,
   no interrupt will be generated from LCD Controller to Cortex-A8?

Q6.In LCDC sample program of newest AM335x Processor SDK,
   initialization of each bits of RASTER_TIMING_2 Register are done from the following APIs.
   -LCDCRasterTimingConfig()
   -LCDCRasterPolarityConfig()
   -LCDCRasterAcbiasConfig()
   Are there any sequence to set each bits of the RASTER_TIMING_2 Register?
   Or we don't need to care the sequence?

Q7.In LCDC sample program of newest AM335x Processor SDK,
   LCD controller never been reset by CLKC_RESET Register of LCDC.
   Should we set the all valid bit to "1"(Reset Enable) at initialization?
  
   By the way, if we reset each module by setting above CLKC_RESET Register,
   how to detect the reset are done?

best regards,
g.f.

  • 0
    TI__Guru**** 393215 points
    Hi,

    The support team have been notified. They will respond here.
  • 0 in reply to Biser Gatchev-XID
    TI__Guru**** 393215 points

    Q1. AM335x Datasheet Section 7.1.1: The timing parameter values specified in this data manual assume the SLEWCTRL bit in each pad control register is configured for fast mode (0b).
    Q2. Hi-Z means input with pullup/pulldown disabled.
    Q3. Yes.
    Q4. Yes.
    Q5. Yes.
    Q5. Interrupts should be disabled via the IRQENABLE_CLEAR register.
    Q6. Which SDK is this?
    Q7. Which SDK is this?

  • 0 in reply to Biser Gatchev-XID
    Guru 15520 points
    Hi Biser,

    Thank you for the reply.

    Q1.
    I understood as that SLEWCTRL bit of all pad control register are set to 0(fast mode) in default.
    But after I connect the AM335xEVM to CCS and checked the default value of each pad control registers,
    the following pad control registers bit[6](SLEWCTRL) was set to 1(Slow mode).
    -conf_uart0_rxd
    -conf_uart0_txd
    -conf_i2c0_sda
    -conf_i2c0_scl
    (all other pad control register was set to fast mode)

    Q2.
    I understood that pullup/down are disabled for Hi-Z pins.
    I also want to know which pullup or down are selected for Hi-Z pins after reset are released.
    I checked a few Hi-Z pins via CCS. It seems that pulldown are selected for default for Hi-Z pins.

    Q5.
    I read LCD Controller chapter of TRM once more again.
    It seems that DMA engine are always necessary and it can't be disabled.
    Because from TRM page.1877 Figure 13-1 "LCDC Controller",
    it seems that there are no way to transfer the data from the external buffer to LCDC internal FIFO by CPU.
    Is my understanding correct?

    Q6.&Q7.
    We are using AM335x PDK v1.0.5 which are inluded in RTOS PRocessor SDK v.3.02.00.05.

    best regards,
    g.f.
  • 0 in reply to g.f.
    TI__Guru**** 393215 points
    Q1. Generally it's not recommended to change default SLEWCTRL settings, as this will have no visible effect on signal quality.
    Q2. ROM code changes some pins from their reset state, depending on the boot sequence chosen.
    Q5. Yes.
    Q6/Q7. I have notified the RTOS team. They will respond here.
  • 0 in reply to Biser Gatchev-XID
    Guru 15520 points
    Hi Biser,

    Thank you for the reply.

    Q1.
    Actually, this question was from my customer.
    They just want to know the default value of conf_<module>_<pin> register bit[6],
    because in TRM it said "Reset value is pad-dependent."

    Q6.&Q7
    Thank you for sending to RTOS team.

    Best regards,
    g.f.
  • 0 in reply to g.f.
    TI__Guru**** 393215 points
    About Q1, I think I answered clearly enough in my last post above.
  • 0 in reply to Biser Gatchev-XID
    Guru 15520 points
    Hi Biser,

    Thank you for the reply.
    I understood about Q1, thank you so much.

    I will wait the answer for Q6/Q7 from RTOS team.

    best regards,
    g.f.