Part Number: DRA744
Referring to the datasheet of Jacinto 6, paragraph 8.5.6.3 ("LJCB_REFN / P Connections") presents the ability to configure two modes of operation for the PCIe clock:
- External Mode Refclk
- Output Mode Refclk
About the latter option:
“In Output REFCLK Mode, the 100MHz clock from the Device’s DPLL_PCIE_REF should be output on the Device’s ljcb_clkn / ljcb_clkp pins and used as the HCSL REFCLK by the link partner. External nearside termination to ground described in Table 8-29 is required on both of the ljcb_clkn / ljcb_clkp outputs in this mode.”
In our application the link partner is a WiFi module with LVPECL clock input:
- is it possible to match a HCSL driver with a LVPECL input by mean of a passive network?
- in this case, how much would be the max trace length?
