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How to configure VENC for non-standard resolution?

Hello.  I need help configuring the DM6446's VENC to support a non-standard resolution.  My goal is to have 1316x480 interlaced digital output (YCC8), and as a first step I want to enable the color bars in the VENC.  Here is my current configuration:

VPBECLK = 50 MHz

; PCR register
sendln "mw 01c72784 0"
pause 1

;# VPSS_CLKCTL
; set to VPBE_CLK input
; turn off DAC clk
sendln "mw 01c40044 0000000A"
pause 1


;# Video Mode Register
;# Digital Video Output = YCC8
;# Interlace
;# SDTV
;# NTSC
;# Master mode (bit 5 = 0)
;# Non-standard timing
;# Normal blanking
;# Normal composite analog output
;# Disable the VENC at this point - enable later
sendln "mw 1c72400 00001212"
pause 1

;# VIDCTL - Video IO Control Register
; 14 VCLK output polarity. 0 = non-inverse, 1 = Inverse
; 13 VCLK output enable. 0=Off, 1=On (Outputs DCLK from VCLK pin)
; 12 VCLK pin output enable.  0=Output, 1=Hi-Z
; YOUT and COUT NOT swapped
sendln "mw 1c72404 00002000"
pause 1

; Setup DCLK.
sendln "mw 1c72464 801"
pause 1
sendln "mw 1c72468 03"
pause 1

; Setup OSDCLK.
sendln "mw 1c7252c 0"
pause 1
sendln "mw 1c72530 1"
pause 1

; Setup Sync Control
sendln "mw 1c7240c f"
pause 1

; Setup YCC Control
; bits 3-2 Set output order
;  x0 (0) - Cb-Y-Cr-Y
;  x1 (4) - Y-Cr-Y-Cb
;  x2 (8) - Cr-Y-Cb-Y
;  x3 (c) - Y-Cb-Y-Cr
sendln "mw 1c72438 0"
pause 1


;=================================
; Display setup
;=================================
; HSPLS
sendln "mw 1c72410 dc"
pause 1

; VSPLS
sendln "mw 1c72414 4"  ; width in hsync pulses of vsync
pause 1

; HINT
sendln "mw 1c72418 c63"
pause 1

; HSTART
sendln "mw 1c7241c 1ea"
pause 1

; HVALID
sendln "mw 1c72420 524"  ; x280=640, x2d0=720, x500=1280, x524=1316, x5a0=1440, x640=1600, x780=1920, xa46=2630
pause 1

; VINT
; Vertical interval (number of lines) is represented by VINT + 1.
sendln "mw 1c72424 20c"  ; x20d=525
pause 1

; VSTART
sendln "mw 1c72428 16"
pause 1

; VSTARTA - for interlaced
sendln "mw 1c72528 00"
pause 1

; VVALID
sendln "mw 1c7242c 1e0"  ; 480 = x1e0
pause 1

; HSDLY
sendln "mw 1c72430 0"
pause 1

; VSDLY
sendln "mw 1c72434 0"
pause 1



;===============================


;# Enable the color bar
sendln "mw 1c72408 100"
pause 1


;# Finally, enable VENC and hope.
sendln "mw 1c72400 00001213"
pause 1

  • Jared7 said:
    need help configuring the DM6446's VENC to support a non-standard resolution.  My goal is to have 1316x480 interlaced digital output (YCC8), and as a first step I want to enable the color bars in the VENC.

    That is a bit of a strange resolution to output, but you should be able to get color bars output by simply having the output enabled and setting the VDPRO.CBMD bit. Are you getting any output or anything close to what you are expecting?

    One reference for configuring the VPBE you may find handy is this application note, though it is a bit old so the software itself is out of date, the appendices A3-5 have some example configurations for HDTV signals you may find of some help as an example.

  • A strange resolution indeed...but that is what I need.

    With the posted configuration, I get quasi-color bars, scrolling vertically, and each bar resembles a two-sided comb.  The bars are right justified, and do not appear to be in the proper order.  My scope will not lock onto the signal when set to trigger on video signals.  On the analog signal, it appears that the sync pulse is the wrong polarity.  Although looking at the VSYNC and HSYNC outputs of DaVinci, VSYNC appears to be 128.1us wide at a frequency of 60 Hz, and HSYNC is 4.4 us wide at a frequency of 15.76 KHz (period of 63.44us).

    If I change the YCC Control settings to output Y-Cr-Y-Cb, and set VSPLS to 0x210 (or greater) I will get color bars that are left justified, that appear to be in the proper order.  The scope will lock onto the analog output signal, which looks like a 8 step staircase, with a negative pulse where I would expect the sync to be.  However, HSYNC is always at the same duty cycle.  VSYNC is always low (as expected by setting it greater than the number of lines).  I would expect HSYNC to vary during the equalization pulses, but I do not see this.

  • I think I need DaVinci to generate a composite sync signal (in reference to my previous statement, "...expect HSYNC to vary during equalization pulses...").  So I set SYNCCTL.VSYNCS = 1 for a composite sync signal, but I do not see any change on the HSYNC output.  I notice that VSYNC now is held low.  Do I need to do something else to get a composite HYSNC signal out on the HYSNC pin?

     

    Any help would be greatly appreciated!