• State Resolved
  • Locked Locked
  • Replies 13 replies
  • Answers 1 answer
  • Subscribers 100 subscribers
  • Views 1967 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DRA626: the GPIO4 of DRA624 can't generate EDMA synchronization event

Alex.Liu
Prodigy 100 points
Part Number: DRA626
Other Parts Discussed in Thread: SYSCONFIG

I am use the DRA624. and I use the GPIO4[8] to input AD's EOC .I want the GPIO4[8] to trigger EDMA to move AD data, but the EDMA didn,t move the AD's data.

I measure the GPIO4 synchronization event signal by OBS_DMA pin, there is no GPIO4 synchronization event pulse is generated.

the associate setting is:

the pin D21 is configed as GPIO by PINCTRL 109, and  the D21 receiver ability is enabled.

the GPIO4[8] is configed as input by GPIO_OE register.

enable the falling edge detection by GPIO_FALLINGDETECT register

enable the GPIO4 interrupt 0 by GPIO_IRQENABLE_SET_0

PS: the interrupt of GPIO4 can generate correctly.

  • 0
    TI__Prodigy 660 points
    Hello,

    I assume you might have already done this but I have to ask:

    Have you mapped the GPIO4 sync event (GPIOEVT4) to any of the EDMA sync inputs? According to the DRA62x TRM, the GPIO4 sync event is NOT mapped by default to any of the EDMA inputs, so you have to program the corresponding EDMA3CC_EVTMUX_x register (part of the Control Module register space) as needed, in order to use this event for trigerring an EDMA transfer.

    For more details, please refer to sections "1.6.5 EDMA Channel Synchronization Events" and "3.1 Control Module" in the DRA62x TRM.

    Regards,
    Vasil
  • 0 in reply to Vasil Kehayov
    Prodigy 100 points

    yes I have already mapped the GPIOEVT4 to edma sync input 22 by EDMA3CC_EVTMUX_19_22.

    I find when I reset the GPIO4 module by GPIO_SYSCONFIG. It can generate only one EDMA sync event .

  • 0 in reply to Alex.Liu
    TI__Mastermind 42515 points
    Hi Alex,

    I have forwarded your question to EDMA expert.

    Regards,
    Yordan
  • 0 in reply to Alex.Liu
    TI__Genius 17720 points
    Alex,
    I'm not expert in DRA6, but you said you get only one DMA event after GPIO module reset. I was just thinking, whether the GPIO interrupt is needing clearing in order to produce further events? I.e. a simple interrupt routine to reset the GPIO4[8] STATUS bit?
  • 0 in reply to Stanislav Stilyanov
    Prodigy 100 points
    I have clear the GPIO4[8] interrupt status bit in interrupt routine.But the GPIO4[8] still can't generate EDMA syn event.
  • 0 in reply to Alex.Liu
    TI__Guru**** 170625 points

    Alex,

    Alex.Liu said:
    yes I have already mapped the GPIOEVT4 to edma sync input 22 by EDMA3CC_EVTMUX_19_22.

    We do not have EDMA3CC_EVTMUX_19_22 register in the DRA62x TRM (SPRUHF4C), see section 3.2 CONTROL_MODULE Registers

    What we have is EDMA3CC_EVTMUX_16_19, EDMA3CC_EVTMUX_20_23, etc

    Could you please specify which EDMA3CC_EVTMUX_x register exactly (at which physical address) you program and what value you wrote in that register?

    Regards,
    Pavel

  • 0 in reply to Pavel Botev
    Prodigy 100 points

    the configuration of GPIO4 and control module is as below：

    register                                                            address                                      value

    PINCNTL109                                                0x081409B0                           0x00060040

    EDMA3CC_EVTMUX_20_23                     0x08140FA4                            0x00310000

    GPIO_OE                                                       0x08420134                            0xFFFFFFFF

    GPIO_IRQENABLE_SET_1                       0x08420038                            0x00000100

    GPIO_FALLINGDETECT                            0x0842014C                           0x00000100

    DMAOBS                                                        0x081416F0                            0x00008070

    PINCNTL183                                                0x08140AD8                           0x000B0200

    the pin which I used is GPIO4[8]. And I use a scope to monitor the GPIO4EVT on DMAOBS PIN

  • 0 in reply to Alex.Liu
    TI__Prodigy 660 points
    Alex,

    Since you're mapping the GPIOEVT4 event to EDMA sync input #22, shouldn't the value of the DMAOBS register be 0x00008016?

    My understanding is that if you set the DMAOBS[7:0] DMAOBS1_SEL bit field to 0x10, you will get EDMA sync event #16 on the dmaobs pin, not event #22. So I think this bit field should be set to 0x16.

    Regards,
    Vasil
  • 0 in reply to Vasil Kehayov
    Prodigy 100 points
    my last reply have a mistake.the actual value I have set is as below.
    register address value
    DMAOBS 0x081416F0 0x00008070
    In the table 3-3 OBS_DMA mapping of DRA624 TRM. the GPIO4EVT numble is 112, so I think the input signal of DMAOBS pin is before EDMA event crossbar. and it is not affect by EDMA_EVTMUX register.
  • 0 in reply to Alex.Liu
    TI__Prodigy 660 points
    Yes, you're right, that should be the correct value. I was looking at the wrong table.

    Regards,
    Vasil
  • 0 in reply to Alex.Liu
    TI__Guru**** 170625 points

    Alex.Liu said:
    EDMA3CC_EVTMUX_20_23                     0x08140FA4                            0x00310000

    This event 22 is reserved in TRM. Can you try to overwrite some existing event (for example 23 TIMER1), will be there any difference?

    Alex.Liu said:
    GPIO_IRQENABLE_SET_1                       0x08420038                            0x00000100

    You are using SET_1 which map to GPIOINT4B in A8, DSP and M3. But we do not have GPIOEVT4A and GPIOEVT4B for EDMA. Can you try with using GPIO_IRQENABLE_SET_0 instead of GPIO_IRQENABLE_SET_1, will be there any difference?


    With EDMA crossbar, the GPIO4 interrupt request is redirect as DMA request. For every raising/falling edge on GPIO4_8 pin, will generate an interrupt, and this interrupt will be redirect as DMA request. EDMA3 should be configurred properly to handle the EDMA event.

    To verify that interrupt request is generated in the GPIO4 module itself, first check the corresponding GPIO_IRQSTATUS_RAW_0/1 and/or GPIO_IRQSTATUS_0/1 register. Once the event occur on that GPIO pin, it should be logged in the IRQSTATUS register, the corresponding bit should transition from 0 to 1.


    Regards,
    Pavel

  • 0 in reply to Pavel Botev
    Prodigy 100 points
    Hi pavel

    I have fixed the problem. the problem is I didn't acknowledge the EDMA event of GPIO4 by GPIO_EOI register.
    when I acknowledge the GPIO4 event by GPIO_EOI. the GPIO4 Edma event can be generated contiously.


    Regards,
    Alex
  • 0 in reply to Alex.Liu
    TI__Mastermind 42515 points
    Hi Alex,

    thanks for the updating the thread with the solution.
    I will close it, but if you have any further issues, you can write here.

    Regards,
    Yordan